Gautham N. Chinya

According to our database1, Gautham N. Chinya authored at least 17 papers between 2006 and 2021.

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Bibliography

2021
Design Considerations for Edge Neural Network Accelerators: An Industry Perspective.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2020
Helper Without Threads: Customized Prefetching for Delinquent Irregular Loads.
CoRR, 2020

2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019

Improving Branch Prediction By Modeling Global History with Convolutional Neural Networks.
CoRR, 2019

Post-silicon CPU adaptation made practical using machine learning.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning.
IEEE Micro, 2018

Programming Spiking Neural Networks on Intel's Loihi.
Computer, 2018

Mapping spiking neural networks onto a manycore neuromorphic architecture.
Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2018

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2011
Bothnia: a dual-personality extension to the Intel integrated graphics driver.
ACM SIGOPS Oper. Syst. Rev., 2011

AstroLIT: enabling simulation-based microarchitecture comparison between Intel® and Transmeta designs.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
Intel nehalem processor core made FPGA synthesizable.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
Intel® atom<sup>TM</sup> processor core made FPGA-synthesizable.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system.
Proceedings of the ACM SIGPLAN 2007 Conference on Programming Language Design and Implementation, 2007

Sequencer virtualization.
Proceedings of the 21th Annual International Conference on Supercomputing, 2007

2006
Multiple Instruction Stream Processor.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006


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