Gaurav Singh
Affiliations:- Intel Corporation, Austin, USA
- State University, Virginia Technology, Virginia Polytechnic Institute, CESCA, FERMAT Lab, Blacksburg, VA, USA
According to our database1,
Gaurav Singh
authored at least 10 papers
between 2005 and 2010.
Collaborative distances:
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Bibliography
2010
Springer, ISBN: 978-1-4419-6480-9, 2010
2009
A Formally Verified Peak-Power Reduction Technique for Hardware Synthesis from Concurrent Action-Oriented Specifications.
J. Low Power Electron., 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2008
Proceedings of the Model Checking Software, 2008
2007
Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications.
J. Low Power Electron., 2007
Algorithms for low power hardware synthesis from Concurrent Action Oriented Specifications (CAOS).
Int. J. Embed. Syst., 2007
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007
Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications.
Proceedings of the Power-aware Computing Systems, 21.01. - 26.01.2007, 2007
2006
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006
2005
An overview of the competitive and adversarial approaches to designing dynamic power management strategies.
IEEE Trans. Very Large Scale Integr. Syst., 2005