Gaurang Upasani
Orcid: 0009-0004-6163-7627
According to our database1,
Gaurang Upasani
authored at least 10 papers
between 2009 and 2024.
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Collaborative distances:
Timeline
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2024
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Bibliography
2024
IEEE Comput. Archit. Lett., 2024
2023
Fifty Years of the International Symposium on Computer Architecture: A Data-Driven Retrospective.
IEEE Micro, 2023
2016
2014
Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2012
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012
2009
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009