Gary William Grewal
Orcid: 0000-0003-0845-6929
According to our database1,
Gary William Grewal
authored at least 89 papers
between 1994 and 2024.
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On csauthors.net:
Bibliography
2024
Proceedings of the Optimization, Learning Algorithms and Applications, 2024
Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024
Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2024
2023
IEEE Des. Test, October, 2023
A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based Algorithms.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Proceedings of the International Conference on Microelectronics, 2023
Proceedings of the International Conference on Field Programmable Technology, 2023
2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
Proceedings of the International Conference on Microelectronics, 2022
2021
ACM Trans. Reconfigurable Technol. Syst., 2021
Proceedings of the 3rd ACM/IEEE Workshop on Machine Learning for CAD, 2021
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021
Using Machine Learning to Predict Operating Frequency During Placement in FPGA Designs.
Proceedings of the International Conference on Microelectronics, 2021
2020
Machine Learning for Congestion Management and Routability Prediction within FPGA Placement.
ACM Trans. Design Autom. Electr. Syst., 2020
Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
2019
Novel Congestion-estimation and Routability-prediction Methods based on Machine Learning for Modern FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2019
Proceedings of the 31st International Conference on Microelectronics, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
ACM Trans. Design Autom. Electr. Syst., 2018
Corrigendum to "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm".
Int. J. Reconfigurable Comput., 2018
Corrigendum to "An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization".
Int. J. Reconfigurable Comput., 2018
Proceedings of the 17th IEEE International Conference on Machine Learning and Applications, 2018
Proceedings of the 30th International Conference on Microelectronics, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
2017
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Hardware accelerators for the K-nearest neighbor algorithm using high level synthesis.
Proceedings of the 29th International Conference on Microelectronics, 2017
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the Advances in Artificial Intelligence, 2017
2016
An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems.
Int. J. Reconfigurable Comput., 2016
An Efficient Framework for Floor-plan Prediction of Dynamic Runtime Reconfigurable Systems.
CoRR, 2016
Design exploration of ASIP architectures for the K-Nearest Neighbor machine-learning algorithm.
Proceedings of the 28th International Conference on Microelectronics, 2016
Proceedings of the IEEE International Conference on Data Mining Workshops, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 21st IEEE International Workshop on Computer Aided Modelling and Design of Communication Links and Networks, 2016
2015
Efficient Mapping and Allocation of Execution Units to Task Graphs using an Evolutionary Framework.
SIGARCH Comput. Archit. News, 2015
J. Comput. Sci., 2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
A Machine-Learning Based Approach for Measuring the Completeness of Online Privacy Policies.
Proceedings of the 14th IEEE International Conference on Machine Learning and Applications, 2015
Proceedings of the 14th IEEE International Conference on Machine Learning and Applications, 2015
2014
Advancing genetic algorithm approaches to field programmable gate array placement with enhanced recombination operators.
Evol. Intell., 2014
Proceedings of the 2014 IEEE International Conference on Data Mining Workshops, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2013
Int. J. Reconfigurable Comput., 2013
An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization.
Int. J. Reconfigurable Comput., 2013
2012
An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C.
VLSI Design, 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
A Sequential Ensemble Classification (SEC) System for Tackling the Problem of Unbalance Learning: A Case Study.
Proceedings of the 11th International Conference on Machine Learning and Applications, 2012
Proceedings of the 11th International Conference on Machine Learning and Applications, 2012
Depictions of genotypic space for evaluating the suitability of different recombination operators.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012
A formal and empirical analysis of recombination for genetic algorithm-based approaches to the FPGA placement problem.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012
2011
Proceedings of the 2011 International Conference on Parallel Processing Workshops, 2011
Using GPUs to accelerate FPGA wirelength estimate for use with complex search operators.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
2010
A Graph-Based I/O Pad Pre-placement Technique for Use with Analytic FPGA Placement Methods.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010
Proceedings of the Genetic and Evolutionary Computation Conference, 2010
An investigation of parallel memetic algorithms for VLSI circuit partitioning on multi-core computers.
Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010
2009
Meta-Heuristic Based Techniques for FPGA Placement: A Study.
Int. J. Comput. Their Appl., 2009
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009
2008
Proceedings of the 26th International Conference on Computer Design, 2008
2007
Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic.
Appl. Intell., 2007
2006
Int. J. Comput. Intell. Appl., 2006
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
Comparing a Genetic Algorithm Penalty Function and Repair Heuristic in the DSP Application Domain.
Proceedings of the IASTED International Conference on Artificial Intelligence and Applications, 2006
2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
An Approximate Solution for Steiner Trees in Multicast Routing.
Proceedings of the International Conference on Artificial Intelligence, 2004
A Fast Hierarchical Approach to FPGA Placement.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors.
SIGARCH Comput. Archit. News, 2003
Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T).
Int. J. Comput. Intell. Appl., 2003
Hierarchical Genetic Algorithms Applied to Datapath Synthesis.
Proceedings of the International Conference on Artificial Intelligence, 2003
Proceedings of the IEEE Congress on Evolutionary Computation, 2003
2002
An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular Networks.
Proceedings of the Advances in Artificial Intelligence, 2002
2001
An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and Binding.
Int. J. Comput. Intell. Appl., 2001
1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI Design.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
1996
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996
1994
Proceedings of the 7th International Symposium on High Level Synthesis, 1994
An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block Synthesis.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
An ILP-based approach to code generation.
Proceedings of the Code Generation for Embedded Processors [Dagstuhl Workshop, Dagstuhl, Germany, August 31, 1994