Gary S. Tyson

Proceedings of the 14th International Conference on Evaluation of Novel Approaches to Software Engineering, 2019

2016

Agave: A benchmark suite for exploring the complexities of the Android software stack.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

2015

Scheduling instruction effects for a statically pipelined processor.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Compilers, 2015

2014

A journey toward obtaining our first NSF S-STEM (scholarship) grant.

[BibT_eX]

[DOI]

Proceedings of the 45th ACM Technical Symposium on Computer Science Education, 2014

2013

Improving processor efficiency by statically pipelining instructions.

[BibT_eX]

[DOI]

Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013

2012

Program Differentiation.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2012

An Overview of Static Pipelining.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2012

2011

ContextProvider: Context awareness for medical monitoring applications.

[BibT_eX]

[DOI]

Michael Mitchell

Christopher R. Meyers

An-I Andy Wang

Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Improving Low Power Processor Efficiency with Static Pipelining.

[BibT_eX]

[DOI]

Proceedings of the 15th Workshop on Interaction between Compilers and Computer Architectures, 2011

2010

Effect of sequences on the shape of protein energy landscapes.

[BibT_eX]

[DOI]

Yue Li

Jinfeng Zhang

Proceedings of the First ACM International Conference on Bioinformatics and Computational Biology, 2010

2009

Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2009

Practical exhaustive optimization phase order exploration and evaluation.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2009

Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE).

[BibT_eX]

[DOI]

Stephen Roderick Hines

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009

Core monitors: monitoring performance in multicore processors.

[BibT_eX]

[DOI]

Proceedings of the 6th Conference on Computing Frontiers, 2009

2008

Enhancing the effectiveness of utilizing an instruction register file.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education.

[BibT_eX]

[DOI]

Renato J. O. Figueiredo

Proceedings of the Collaborative Computing: Networking, 2008

2007

Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems.

[BibT_eX]

[DOI]

Michael J. Geiger

Sally A. McKee

Trans. High Perform. Embed. Archit. Compil., 2007

Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache.

[BibT_eX]

[DOI]

Stephen Hines

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

Addressing instruction fetch bottlenecks by using an instruction register file.

[BibT_eX]

[DOI]

Stephen Roderick Hines

Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Evaluating Heuristic Optimization Phase Order Search Algorithms.

[BibT_eX]

[DOI]

Prasad A. Kulkarni

Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

Facilitating compiler optimizations through the dynamic mapping of alternate register structures.

[BibT_eX]

[DOI]

Christopher Zimmer

Stephen Roderick Hines

Prasad A. Kulkarni

Proceedings of the 2007 International Conference on Compilers, 2007

2006

High-quality ISA synthesis for low-power cache designs in embedded microprocessors.

[BibT_eX]

[DOI]

IBM J. Res. Dev., 2006

In search of near-optimal optimization phase orderings.

[BibT_eX]

[DOI]

Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Reducing the cost of conditional transfers of control by using comparison specifications.

[BibT_eX]

[DOI]

Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Exhaustive Optimization Phase Order Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

Adapting compilation techniques to enhance the packing of instructions into registers.

[BibT_eX]

[DOI]

Stephen Hines

Proceedings of the 2006 International Conference on Compilers, 2006

2005

An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows.

[BibT_eX]

[DOI]

Stephen Hines

Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

Improving Program Efficiency by Packing Instructions into Registers.

[BibT_eX]

[DOI]

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation.

[BibT_eX]

[DOI]

Michael J. Geiger

Sally A. McKee

Proceedings of the High Performance Embedded Architectures and Compilers, 2005

Drowsy region-based caches: minimizing both dynamic and static power dissipation.

[BibT_eX]

[DOI]

Michael J. Geiger

Sally A. McKee

Proceedings of the Second Conference on Computing Frontiers, 2005

2004

A Prefetch Taxonomy.

[BibT_eX]

[DOI]

Viji Srinivasan

IEEE Trans. Computers, 2004

FITS: framework-based instruction-set tuning synthesis for embedded application specific processors.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2001

Improving Bandwidth Utilization using Eager Writeback.

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2001

Allocation by Conflict: A Simple Effective Multilateral Cache Management Scheme.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Branch History Guided Instruction Prefetching.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Stack Value File: Custom Microarchitecture for the Stack.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000

Improving BTB performance in the presence of DLLs.

[BibT_eX]

[DOI]

Stevan A. Vlaovic

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Eager writeback - a technique for improving bandwidth utilization.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Quantifying instruction-level parallelism limits on an EPIC architecture.

[BibT_eX]

[DOI]

Youfeng Wu

Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

Instruction overhead and data locality effects in superscalar processors.

[BibT_eX]

[DOI]

Murali Annavaram

Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

Region-based caching: an energy-delay efficient memory architecture for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Conference on Compilers, 2000

[BibT_eX]

[DOI]

Mikhail Smelyanskiy

Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

1999

Active Management of Data Caches by Exploiting Reuse Information.

[BibT_eX]

[DOI]

Edward S. Tam

Jude A. Rivers

Vijayalakshmi Srinivasan

IEEE Trans. Computers, 1999

The limits of instruction level parallelism in SPEC95 applications.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 1999

A high level simulator integrated with the Mirv compiler.

[BibT_eX]

[DOI]

Krisztián Flautner

SIGARCH Comput. Archit. News, 1999

Performance Limits of Trace Caches.

[BibT_eX]

[DOI]

Matt Postiff

J. Instr. Level Parallelism, 1999

Memory Renaming: Fast, Early and Accurate Processing of Memory Communication.

[BibT_eX]

[DOI]

Todd M. Austin

Int. J. Parallel Program., 1999

Classifying load and store instructions for memory renaming.

[BibT_eX]

[DOI]

Proceedings of the 13th international conference on Supercomputing, 1999

1998

Computer architecture instruction at the University of Michigan.

[BibT_eX]

[DOI]

Steven K. Reinhardt

Proceedings of the 1998 workshop on Computer architecture education, 1998

Analyzing the Working Set Characteristics of Branch Execution.

[BibT_eX]

[DOI]

Sangwook P. Kim

Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

mlcache: A Flexible Multi-Lateral Cache Simulator.

[BibT_eX]

[DOI]

Proceedings of the MASCOTS 1998, 1998

Utilizing Reuse Information in Data Cache Management.

[BibT_eX]

[DOI]

Proceedings of the 12th international conference on Supercomputing, 1998

Evaluating the performance of active cache management schemes.

[BibT_eX]

[DOI]

Edward S. Tam

Jude A. Rivers

Vijayalakshmi Srinivasan

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

Managing data caches using selective cache line replacement.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1997

Improving the Accuracy and Performance of Memory Communication Through Renaming.

[BibT_eX]

[DOI]

Todd M. Austin

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

On High-Bandwidth Data Cache Design for Multi-Issue Processors.

[BibT_eX]

[DOI]

Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

1996

Evaluating the Effects of Predicated Execution on Branch Prediction.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1996

1995

A modified approach to data cache management.

[BibT_eX]

[DOI]

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1994

Code scheduling for multiple instruction stream architectures.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 1994

The effects of predicated execution on branch prediction.

[BibT_eX]

[DOI]

Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors.

[BibT_eX]

[DOI]

Andrew R. Pleszkun

Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1993

Techniques for extracting instruction level parallelism on MIMD architectures.

[BibT_eX]

[DOI]

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992

MISC: a Multiple Instruction Stream Computer.

[BibT_eX]

[DOI]

Andrew R. Pleszkun

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Modifying VM hardware to reduce address pin requirements.

[BibT_eX]

[DOI]

Arvin Park