Gary Pomichter
According to our database1,
Gary Pomichter
authored at least 7 papers
between 2001 and 2010.
Collaborative distances:
Collaborative distances:
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Bibliography
2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2007
Proceedings of the 2007 IEEE International Test Conference, 2007
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining.
IEEE J. Solid State Circuits, 2005
2002
IBM J. Res. Dev., 2002
2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001