Gary Lauterbach

According to our database, Gary Lauterbach authored at least 11 papers between 1994 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

The Path to Successful Wafer-Scale Integration: The Cerebras Story.

Gary Lauterbach

IEEE Micro, 2021

2013

A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O.

Kshitij Sudan, Saisanthosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, Rajeev Balasubramonian

Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

2011

SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips.

Ashutosh Dhodapkar, Gary Lauterbach, Sean Lie, Dhiraj Mallick, Jim Bauman, Sundar Kanthadai, Toru Kuzuhara, Gene Shen, Min Xu, Chris Zhang

Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011

2005

Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication.

Robert J. Drost, Craig Forrest, Bruce Guenin, Ron Ho, Ashok V. Krishnamoorthy, Danny Cohen, John E. Cunningham, Bernard Tourancheau, Arthur Zingher, Alex Chow, Gary Lauterbach, Ivan E. Sutherland

Proceedings of the 13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 2005

2003

Robust Highly-Connected Direct Interconnection Network Topologies.

Ilya Sharapov, Gary Lauterbach, Stephen P. Crago

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

2000

A third-generation SPARC V9 64-b microprocessor.

Raymond A. Heald, Kathirgamar Aingaran, Chaim Amir, Michael Ang, Michael Boland, Pankaj Dixit, Gary Gouldsberry, Dale Greenley, Joel Grinberg, Jason M. Hart, Tim Horel, Wen-Jay Hsu, James M. Kaku, Chin Kim, Song Kim, Fabian Klass, Hang Kwan, Gary Lauterbach, Roger Lo, Hugh McIntyre, Anup Mehta, David Murata, Sophie Nguyen, Yet-Ping Pai, Subeer Patel, Ken Shin, Kenway Tam, Sai Vishwanthaiah, John Wu, Gin Yee, Eileen You

IEEE J. Solid State Circuits, 2000

1999

UltraSPARC-III: designing third-generation 64-bit performance.

Tim Horel, Gary Lauterbach

IEEE Micro, 1999

Vying for the Lead in High-Performance Processors (Interview).

Gary Lauterbach

Computer, 1999

1998

64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency.

Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino

IEEE J. Solid State Circuits, 1998

Low Load Latency Through Sum-Addressed Memory (SAM).

William L. Lynch, Gary Lauterbach, Joseph I. Chamdani

Proceedings of the 25th Annual International Symposium on Computer Architecture, 1998

1994

Accelerating Architectural Simulation by Parallel Execution of Trace Samples.

Gary Lauterbach

Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994