Gary B. Bronner

According to our database, Gary B. Bronner authored at least 3 papers between 1989 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2007

Optimization of silicon technology for the IBM System z9.

Daniel J. Poindexter, Scott R. Stiffler, Philip T. Wu, Paul D. Agnello, Thomas Ivers, Shreesh Narasimha, Thomas B. Faure, Jed H. Rankin, David A. Grosch, Marc D. Knox, Daniel C. Edelstein, Mukesh Khare, Gary B. Bronner, Hyun-Jang Nam, Shahid A. Butt

IBM J. Res. Dev., 2007

2002

Challenges and future directions for the scaling of dynamic random-access memory (DRAM).

Jack A. Mandelman, Robert H. Dennard, Gary B. Bronner, John K. DeBrosse, Rama Divakaruni, Yujun Li, Carl J. Raden

IBM J. Res. Dev., 2002

1989

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing.

Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano

IEEE J. Solid State Circuits, October, 1989