Gary A. Van Huben

According to our database1, Gary A. Van Huben authored at least 7 papers between 1997 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Server-class DDR3 SDRAM memory buffer chip.
IBM J. Res. Dev., 2012

2007
High-speed source-synchronous interface for the IBM System z9 processor.
IBM J. Res. Dev., 2007

Formal Verification of Partial Good Self-Test Fencing Structures.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006
Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning.
Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

2004
Processor subsystem interconnect architecture for a large symmetric multiprocessing system.
IBM J. Res. Dev., 2004

1999
PLL modeling and verification in a cycle-simulation environment.
IBM J. Res. Dev., 1999

1997
The role of two-cycle simulation in the S/390 verification process.
IBM J. Res. Dev., 1997


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