Garrett S. Rose

Orcid: 0000-0003-3070-4087

Affiliations:
  • University of Tennessee, Knoxville, USA


According to our database1, Garrett S. Rose authored at least 151 papers between 2004 and 2024.

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Bibliography

2024
Hardware software co-design for leveraging STDP in a memristive neuroprocessor.
Neuromorph. Comput. Eng., 2024

SpiCS-Net: Circuit Switched Network on Chip for Area-Efficient Spiking Recurrent Neural Networks.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Embracing the Hairball: An Investigation of Recurrence in Spiking Neural Networks for Control.
Proceedings of the Neuro Inspired Computational Elements Conference, 2024

Leveraging Sparsity of SRNNs for Reconfigurable and Resource-Efficient Network-on-Chip.
Proceedings of the Neuro Inspired Computational Elements Conference, 2024

Evaluation of Neuron Parameters on the Performance of Spiking Neural Networks and Neuromorphic Hardware.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Message from the Technical Program Chairs; ISVLSI 2024.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Maximizing Efficiency of SNN-Based Reservoir Computing via NoC-Assisted Dimensionality Reduction.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Hardware-Application Co-Design to Evaluate the Performance of an STDP-based Reservoir Computer.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

In-Sensor Motion Recognition with Memristive System and Light Sensing Surfaces.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

A Memristive Reconfigurable Neuromorphic Array for Neuro-Inspired Dynamic Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

HfO2-Based Synaptic Spiking Neural Network Evaluation to Optimize Design and Testing Cost.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

AnSpiCS-Net: Reconfigurable Network-on-Chip for Analog Spiking Recurrent Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
An Efficient and Accurate Memristive Memory for Array-Based Spiking Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Optimizations for a Current-Controlled Memristor- Based Neuromorphic Synapse Design.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

Spike-based Neuromorphic Computing for Next-Generation Computer Vision.
CoRR, 2023

Reimagining Sense Amplifiers: Harnessing Phase Transition Materials for Current and Voltage Sensing.
CoRR, 2023

Functional Specification of the RAVENS Neuroprocessor.
CoRR, 2023

Enhanced Read Resolution in Reconfigurable Memristive Synapses for Spiking Neural Networks.
CoRR, 2023

A Single Chip SPAD Based Vision Sensing System With Integrated Memristive Spiking Neuromorphic Processing.
IEEE Access, 2023

Energy Efficient and High-Performance Synaptic Operating Point Evaluation for SNN Applications.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Homeostatic Plasticity in a Leaky Integrate and Fire Neuron Using Tunable Leak.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Spike-Driven Synaptic Plasticity for a Memristive Neuromorphic Core.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Spike-Timing-Dependent Plasticity for a Hafnium-Oxide Memristive Synapse.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Algorithm and Application Impacts of Programmable Plasticity in Spiking Neuromorphic Hardware.
Proceedings of the 2023 International Conference on Neuromorphic Systems, 2023

Reliability Analysis of Memristive Reservoir Computing Architecture.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

RFAM: RESET-Failure-Aware-Model for HfO2-based Memristor to Enhance the Reliability of Neuromorphic Design.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A Mixed-Signal Short-Term Plasticity Implementation for a Current-Controlled Memristive Synapse.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A Runtime-Reconfigurable Hardware Encoder for Spiking Neural Networks.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Evaluating Neuron Models through Application-Hardware Co-Design.
Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022
Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things.
ACM J. Emerg. Technol. Comput. Syst., 2022

Unsupervised Digit Recognition Using Cosine Similarity In A Neuromemristive Competitive Learning System.
ACM J. Emerg. Technol. Comput. Syst., 2022

Disclosure of a Neuromorphic Starter Kit.
CoRR, 2022

The Case for RISP: A Reduced Instruction Spiking Processor.
CoRR, 2022

A Generalized Workflow for Creating Machine Learning-Powered Compact Models for Multi-State Devices.
IEEE Access, 2022

A Framework to Enable Top-Down Co-Design of Neuromorphic Systems for Real-World Applications.
Proceedings of the NICE 2022: Neuro-Inspired Computational Elements Conference, 2022

STDP Based Online Learning for a Current-Controlled Memristive Synapse.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Compact Model for the Variable Switching Dynamics of HfO2 Memristors.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

On-Chip Interface for Event based Sensor and Spiking Neuromorphic Processing.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

Variation-aware Design Space Exploration of Mott Memristor-based Neuristors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Programmable Refractory Period Implementations in a Mixed-Signal Integrate-And-Fire Neuron.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Benchmark Comparisons of Spike-based Reconfigurable Neuroprocessor Architectures for Control Applications.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A system design perspective on neuromorphic computer processors.
Neuromorph. Comput. Eng., 2021

Design of a Robust Memristive Spiking Neuromorphic System with Unsupervised Learning in Hardware.
ACM J. Emerg. Technol. Comput. Syst., 2021

Design of an Enhanced Reconfigurable Chaotic Oscillator using G4FET-NDR Based Discrete Map.
CoRR, 2021

Capacitor-Less Memristive Integrate-and-Fire Neuron with Stochastic Behavior.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Scaling Constraints for Memristor-based Programmable Interconnect in Reconfigurable Computing Arrays.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

A Multi-Context Neural Core Design for Reconfigurable Neuromorphic Arrays.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020
A Chaos-Based Complex Micro-instruction Set for Mitigating Instruction Reverse Engineering.
J. Hardw. Syst. Secur., 2020

Device-aware Circuit Design for Robust Memristive Neuromorphic Systems with STDP-based Learning.
ACM J. Emerg. Technol. Comput. Syst., 2020

Towards Synaptic Behavior of Nanoscale ReRAM Devices for Neuromorphic Computing Applications.
ACM J. Emerg. Technol. Comput. Syst., 2020

A Secure Back-up and Restore for Resource-Constrained IoT based on Nanotechnology.
CoRR, 2020

Single Photon Avalanche Diode based Vision Sensor with On-Chip Memristive Spiking Neuromorphic Processing.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Circuit Techniques for Efficient Implementation of Memristor Based Reservoir Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Scaled-up Neuromorphic Array Communications Controller (SNACC) for Large-scale Neural Networks.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Automated Design of Neuromorphic Networks for Scientific Applications at the Edge.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

GRANT: Ground-Roaming Autonomous Neuromorphic Targeter.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

2019
A Secure Integrity Checking System for Nanoelectronic Resistive RAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019

A Review of Spiking Neuromorphic Hardware Communication Systems.
IEEE Access, 2019

Design of a Lightweight Reconfigurable PRNG Using Three Transistor Chaotic Map.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Design Considerations for Insulator Metal Transition based Artificial Neurons.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Multi-Driver Write Scheme for Reliable and Energy Efficient 1S1R ReRAM Crossbar Arrays.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Fabrication and Performance of Hybrid ReRAM-CMOS Circuit Elements for Dynamic Neural Networks.
Proceedings of the International Conference on Neuromorphic Systems, 2019

Stochasticity in Neuromorphic Computing: Evaluating Randomness for Improved Performance.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A Scan Register Based Access Scheme for Multilevel Non-Volatile Memristor Memory.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Memristor Crossbar PUF based Lightweight Hardware Security for IoT.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

On the Theoretical Analysis of Memristor based True Random Number Generator.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Design for Eliminating Operation Specific Power Signatures from Digital Logic.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Design Considerations for Memristive Crossbar Physical Unclonable Functions.
ACM J. Emerg. Technol. Comput. Syst., 2018

A Study of Complex Deep Learning Networks on High-Performance, Neuromorphic, and Quantum Computers.
ACM J. Emerg. Technol. Comput. Syst., 2018

Practical realisation of a return map immune Lorenz-based chaotic stream cipher in circuitry.
IET Comput. Digit. Tech., 2018

Memristive Mixed-Signal Neuromorphic Systems: Energy-Efficient Learning at the Circuit-Level.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Adiabatic Quantum Computation Applied to Deep Learning Networks.
Entropy, 2018

Nanoelectronic Security Designs for Resource-Constrained Internet of Things Devices: Finding Security Solutions with Nanoelectronic Hardwares.
IEEE Consumer Electron. Mag., 2018

A Practical Sense Amplifier Design for Memristive Crossbar Circuits (PUF).
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Design of a Reconfigurable Chaos Gate with Enhanced Functionality Space in 65nm CMOS.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A Mixed-Mode Neuron with On-chip Tunability for Generic Use in Memristive Neuromorphic Systems.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A bi-memristor synapse with spike-timing-dependent plasticity for on-chip learning in memristive neuromorphic systems.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

High-Level Simulation for Spiking Neuromorphic Computing Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Novel Scan-In Scheme for CMOS/ReRAM Programmable Logic Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Neuromorphic Array Communications Controller to Support Large-Scale Neural Networks.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

Chaos computing for mitigating side channel attack.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Energy and Area Efficiency in Neuromorphic Computing for Resource Constrained Devices.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A Soft-Matter Biomolecular Memristor Synapse for Neuromorphic Systems.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

2017
A Survey of Neuromorphic Computing and Neural Networks in Hardware.
CoRR, 2017

Evaluating online-learning in memristive neuromorphic circuits.
Proceedings of the Neuromorphic Computing Symposium, 2017

Neuromorphic computing for temporal scientific data classification.
Proceedings of the Neuromorphic Computing Symposium, 2017

A programming framework for neuromorphic systems with emerging technologies.
Proceedings of the 4th ACM International Conference on Nanoscale Computing and Communication, 2017

A synchronized axon hillock neuron for memristive neuromorphic systems.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A mixed-signal approach to memristive neuromorphic system design.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Design techniques for in-field memristor forming circuits.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Exploiting Memristive Crossbar Memories as Dual-Use Security Primitives in IoT Devices.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A practical hafnium-oxide memristor model suitable for circuit design and simulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A Unified Hardware/Software Co-Design Framework for Neuromorphic Computing Devices and Applications.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Techniques for Improved Reliability in Memristive Crossbar PUF Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A Designer's Rationale for Nanoelectronic Hardware Security Primitives.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

An Application Development Platform for neuromorphic computing.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

Sneak path enabled authentication for memristive crossbar memories.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Security Meets Nanoelectronics for Internet of Things Applications.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Fault Analysis-Based Logic Encryption.
IEEE Trans. Computers, 2015

Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors.
IEEE Trans. Computers, 2015

Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications.
Proc. IEEE, 2015

A two-dimensional chaotic logic gate for improved computer security.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Performance analysis of a memristive crossbar PUF design.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Hardware-Based Computational Intelligence for Size, Weight, and Power Constrained Environments.
Proceedings of the Network Science and Cybersecurity, 2014

Nanoelectronics and Hardware Security.
Proceedings of the Network Science and Cybersecurity, 2014

Design of Neuromorphic Architectures with Memristors.
Proceedings of the Network Science and Cybersecurity, 2014

Memristor Crossbar-Based Neuromorphic Computing System: A Case Study.
IEEE Trans. Neural Networks Learn. Syst., 2014

On designing circuit primitives for cortical processors with memristive hardware.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

A Chaos-Based Arithmetic Logic Unit and Implications for Obfuscation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2013
Memristor-Based Neural Logic Blocks for Nonlinearly Separable Functions.
IEEE Trans. Computers, 2013

Foundations of memristor based PUF architectures.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

A write-time based memristive PUF for hardware security applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

BSB training scheme implementation on memristor-based circuit.
Proceedings of the 2013 IEEE Symposium on Computational Intelligence for Security and Defense Applications, 2013

Hardware security strategies exploiting nanoelectronic circuits.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

An Energy-Efficient Memristive Threshold Logic Circuit.
IEEE Trans. Computers, 2012

Leveraging Memristive Systems in the Construction of Digital Logic Circuits.
Proc. IEEE, 2012

Design Considerations for Multilevel CMOS/Nano Memristive Memory.
ACM J. Emerg. Technol. Comput. Syst., 2012

Nanoelectronic Solutions for Hardware Security.
IACR Cryptol. ePrint Arch., 2012

Exploiting memristive device behavior for emerging digital logic and memory applications.
Proceedings of the IEEE 25th International SOC Conference, 2012

RRAM-based adaptive neural logic block for implementing non-linearly separable functions in a single layer.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Nano-PPUF: A Memristor-Based Security Primitive.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Memristor crossbar based hardware realization of BSB recall function.
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012

Hardware realization of BSB recall function using memristor crossbar arrays.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
3D NOC for many-core processors.
Microelectron. J., 2011

Introduction to Special Issue: Highlights of NANOARCH'09.
ACM J. Emerg. Technol. Comput. Syst., 2011

An Approach to Tolerate Process Related Variations in Memristor-Based Applications.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Exploiting memristance for low-energy neuromorphic computing hardware.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Parallel memristors: Improving variation tolerance in memristive digital circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A read-monitored write circuit for 1T1M multi-level memristor memories.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A hierarchical 3-D floorplanning algorithm for many-core CMP networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A low-power memristive neuromorphic circuit utilizing a global/local training mechanism.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

2010
Memristor based programmable threshold logic array.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Overview: Memristive devices, circuits and systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design considerations for variation tolerant multilevel CMOS/Nano memristor memory.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Inversion schemes for sublithographic programmable logic arrays.
IET Comput. Digit. Tech., 2009

Non-overlapping transition encoding for global on-chip interconnect.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

The effects of logic partitioning in a majority logic based CMOS-NANO FPGA.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

A dual-MOSFET equivalent resistor thermal sensor.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
A Programmable Majority Logic Array Using Molecular Scale Electronics.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Designing CMOS/molecular memories while considering device parameter variations.
ACM J. Emerg. Technol. Comput. Syst., 2007

On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Hybrid CMOS/Molecular Electronic Circuits.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Design approaches for hybrid CMOS/molecular memory based on experimental device data.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2004
Large-signal two-terminal device model for nanoelectronic circuit analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2004


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