Garam Choi
According to our database1,
Garam Choi
authored at least 4 papers
between 2022 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2022
2023
2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2024
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications.
IEEE J. Solid State Circuits, October, 2024
2023
QLC Programmable 3D Ferroelectric NAND Flash Memory by Memory Window Expansion using Cell Stack Engineering.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
Proceedings of the IEEE International Memory Workshop, 2022