Ganghee Lee

Orcid: 0000-0001-7612-1579

According to our database1, Ganghee Lee authored at least 15 papers between 2003 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2018
Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems.
ACM Trans. Reconfigurable Technol. Syst., 2018

Fault Recovery Time Analysis for Coarse-Grained Reconfigurable Architectures.
ACM Trans. Embed. Comput. Syst., 2018

From C to Fault-Tolerant FPGA-Based Systems.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2014
Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture.
IEEE Trans. Dependable Secur. Comput., 2014

2011
Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2010
Communication architecture design for reconfigurable multimedia SoC platform.
Des. Autom. Embed. Syst., 2010

Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, 2010

Thermal-aware fault-tolerant system design with coarse-grained reconfigurable array architecture.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2009
Coarse-grained reconfigurable architecture for multiple application domains: a case study.
Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009

2008
SoCDAL: System-on-chip design AcceLerator.
ACM Trans. Design Autom. Electr. Syst., 2008

2007
Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

2003
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
Proceedings of the 2003 Design, 2003

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design.
Proceedings of the Embedded Software for SoC, 2003


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