Ganga Ram Mishra

According to our database1, Ganga Ram Mishra authored at least 6 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

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Bibliography

2023
FPGA-based Hardware Classifier for Diabetic Sensorimotor Polyneuropathy Severity Assessment.
Proceedings of the First International Workshop on Artificial Intelligence: Empowering Sustainable Development co-located with First International Conference on Artificial Intelligence: Towards Sustainable Intelligence (AI4S-2023), 2023

2019
High-Throughput, Area-Efficient Architecture of 2-D Block FIR Filter Using Distributed Arithmetic Algorithm.
Circuits Syst. Signal Process., 2019

2017
Realisation of optimised eight-bit binary shifter using reversible logic approach.
Int. J. Serv. Technol. Manag., 2017

2016
Performance parameters optimization and implementation of adder/subtractor circuit using reversible logic approach.
Proceedings of the 11th International Conference on Industrial and Information Systems, 2016

Analysis and design of single ended SRAM cell for low-power operation.
Proceedings of the 11th International Conference on Industrial and Information Systems, 2016

2015
A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate.
Int. J. Bus. Data Commun. Netw., 2015


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