Gang Wang

Affiliations:
  • Intuit Inc., Mountain View, CA, USA
  • University of California, Santa Barbara, Department of Electrical and Computer Engineering, CA, USA


According to our database1, Gang Wang authored at least 15 papers between 2004 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2010
Security Primitives for Reconfigurable Hardware-Based Systems.
ACM Trans. Reconfigurable Technol. Syst., 2010

2007
Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization.
ACM Trans. Design Autom. Electr. Syst., 2007

Ant Colony Optimizations for Resource- and Timing-Constrained Operation Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Moats and Drawbridges: An Isolation Primitive for Reconfigurable Hardware Based Systems.
Proceedings of the 2007 IEEE Symposium on Security and Privacy (S&P 2007), 2007

Combining static and dynamic defect-tolerance techniques for nanoscale memory systems.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Statistical Analysis and Design of HARP FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Application partitioning on programmable platforms using the ant colony optimization.
J. Embed. Comput., 2006

On the use of Bloom filters for defect maps in nanocomputing.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Defect-Tolerant Nanocomputing Using Bloom Filters.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Design space exploration using time and resource duality with the ant colony optimization.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Storage assignment during high-level synthesis for configurable architectures.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Instruction scheduling using <i>MAX-MIN</i> ant system optimization.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

HARP: hard-wired routing pattern FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Data Partitioning and Optimizations for Reconfigurable Architectures.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005

2004
A High Performance Application Representation for Reconfigurable Systems.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004


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