Gang-Ryung Uh

According to our database1, Gang-Ryung Uh authored at least 21 papers between 1997 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Facilitating the Bootstrapping of a New ISA.
Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, 2023

2015
Optimizing Transfers of Control in the Static Pipeline Architecture.
Proceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, 2015

Scheduling instruction effects for a statically pipelined processor.
Proceedings of the 2015 International Conference on Compilers, 2015

2013
Improving processor efficiency by statically pipelining instructions.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2013

2012
An Overview of Static Pipelining.
IEEE Comput. Archit. Lett., 2012

2011
Improving Low Power Processor Efficiency with Static Pipelining.
Proceedings of the 15th Workshop on Interaction between Compilers and Computer Architectures, 2011

2007
Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors.
Proceedings of the Compiler Construction, 16th International Conference, 2007

2006
Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs.
Proceedings of the Emerging Directions in Embedded and Ubiquitous Computing, 2006

2005
Compiler transformations for effectively exploiting a zero overhead loop buffer.
Softw. Pract. Exp., 2005

Branch elimination by condition merging.
Softw. Pract. Exp., 2005

2004
Code optimizations for a VLIW-style network processing unit.
Softw. Pract. Exp., 2004

Tuning the WCET of Embedded Applications.
Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2004), 2004

2003
Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Branch Elimination via Multi-variable Condition Merging.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

2002
Efficient and effective branch reordering using profile data.
ACM Trans. Program. Lang. Syst., 2002

Experience with a retargetable compiler for a commercial network processor.
Proceedings of the International Conference on Compilers, 2002

2000
Techniques for Effectively Exploiting a Zero Overhead Loop Buffer.
Proceedings of the Compiler Construction, 9th International Conference, 2000

1999
Effectively Exploiting Indirect Jumps.
Softw. Pract. Exp., 1999

Effective Exploitation of a Zero Overhead Loop Buffer.
Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, 1999

1998
Improving Performance by Branch Reordering.
Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), 1998

1997
Coalescing Conditional Branches into Efficient Indirect Jumps.
Proceedings of the Static Analysis, 4th International Symposium, 1997


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