Gang Li

Orcid: 0000-0001-9133-8282

Affiliations:

Wenzhou University, College of Electrical and Electronic Engineering, China
Ningbo University, Institute of Circuits and Systems Institude of Circuits and Systems, Zhejiang, China

According to our database¹, Gang Li authored at least 25 papers between 2014 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2024

SI PUF: An SRAM and Inverter-Based PUF With a Bit Error Rate of 0.0053% and 0.073/0.042 pJ/bit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Bagua Protocol: A Whole-Process Configurable Protocol for IoT Sensing Devices Security Based on Strong PUF.

[BibT_eX]

[DOI]

Ziyu Zhou

Pengjun Wang

Gang Li

IEEE Internet Things J., January, 2024

Anti-machine-learning-attack strong PUF design based on multi-path delay selection strategy.

[BibT_eX]

[DOI]

Microelectron. J., 2024

PN-APUF: A MOSFET threshold loss based strong arbiter PUF with double-edge sampling.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2024

2023

Machine learning attacks resistant strong PUF design utilizing response obfuscates challenge with lower hardware overhead.

[BibT_eX]

[DOI]

Microelectron. J., December, 2023

Design of a Novel Self-Test-on-Chip Interface ASIC for Capacitive Accelerometers.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

PI PUF: A Processor-Intrinsic PUF for IoT.

[BibT_eX]

[DOI]

Comput. Electr. Eng., January, 2023

A challenge-screening strategy for enhancing the stability of strong PUF based on machine learning.

[BibT_eX]

[DOI]

Ziyu Zhou

Gang Li

Pengjun Wang

Microelectron. J., 2023

A greedy algorithm based Compensation Circuit for Optimizing the Output Statistics of APUF.

[BibT_eX]

[DOI]

Jiana Lian

Pengjun Wang

Gang Li

Microelectron. J., 2023

A highly stable XOR APUF based on deviation signal screening mechanism.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2023

Design of PUF Circuit Based on Charge Leakage of Cascade Dynamic Gate.

[BibT_eX]

[DOI]

Xudong Wu

Gang Li

Pengjun Wang

Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Compact Weak PUF Circuit Based on Random Process Deviations of Amplifier Chain.

[BibT_eX]

[DOI]

Pengjun Wang

Yuanfeng Xie

Gang Li

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022

A compact weak PUF circuit based on MOSFET subthreshold leakage current.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2022

A Novel Machine Learning Attack Resistant APUF with Dual-Edge Acquisition.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021

A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

A 0.004% resolution & SAT.

[BibT_eX]

[DOI]

Integr., 2021

Matrix Encryption based Anti-Machine Learning Attack Algorithm for Strong PUF.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

2019

An Obfuscated Challenge Design for APUF to Resist Machine Learning Attacks.

[BibT_eX]

[DOI]

Bo Chen

Pengjun Wang

Gang Li

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

High performance bistable weak physical unclonable function for IoT security.

[BibT_eX]

[DOI]

Gang Li

Pengjun Wang

Huihong Zhang

IEICE Electron. Express, 2018

2017

A multi-port low-power current mode PUF using MOSFET current-division deviation in 65 nm technology.

[BibT_eX]

[DOI]

Microelectron. J., 2017

A highly reliable lightweight PUF circuit with temperature and voltage compensated for secure chip identification.

[BibT_eX]

[DOI]

Gang Li

Pengjun Wang

Yuejun Zhang

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Design of ternary pulsed reversible counter based on CNFET.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015

Design of power-up and arbiter hybrid physical unclonable functions in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Design of threshold dominant delay Physical Unclonable Functions in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Gang Li

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