Ganesh S. Dasika
According to our database1,
Ganesh S. Dasika
authored at least 20 papers
between 2003 and 2021.
Collaborative distances:
Collaborative distances:
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Bibliography
2021
Proceedings of the IEEE International Symposium on Workload Characterization, 2021
2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
2014
A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
IEEE Trans. Computers, 2012
2011
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation".
IEEE J. Solid State Circuits, 2011
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation.
IEEE J. Solid State Circuits, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 2010 International Conference on Compilers, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
Bridging the computation gap between programmable processors and hardwired accelerators.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
2008
Proceedings of the 45th Design Automation Conference, 2008
2005
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.
IEEE Trans. Computers, 2005
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005
2003
Increasing the number of effective registers in a low-power processor using a windowed register file.
Proceedings of the International Conference on Compilers, 2003