Ganesh R. Saripalli

According to our database, Ganesh R. Saripalli authored at least 2 papers between 2012 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

A 14b 750MS/s DAC in 20nm CMOS with <-168dBm/Hz noise floor beyond Nyquist and 79dBc SFDR utilizing a low glitch-noise hybrid R-2R architecture.

Sang Min Lee, Dongwon Seo, Shahin Mehdizad Taleie, Derui Kong, Michael Joseph McGowan, Tongyu Song, Ganesh R. Saripalli, Jenny Kuo, Seyfi S. Bazarjani

Proceedings of the Symposium on VLSI Circuits, 2015

2012

Clock-Phase-Noise-Induced TX Leakage Estimation of a Baseband Wireless Transmitter DAC.

Sang Min Lee, Shahin Mehdizad Taleie, Ganesh R. Saripalli, Dongwon Seo

IEEE Trans. Circuits Syst. II Express Briefs, 2012