Ganesh Lakshminarayana

According to our database, Ganesh Lakshminarayana authored at least 48 papers between 1996 and 2006.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2006

The LOTTERYBUS on-chip communication architecture.

Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana

IEEE Trans. Very Large Scale Integr. Syst., 2006

2005

Memory binding for performance optimization of control-flow intensive behavioral descriptions.

Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2005

Input space-adaptive optimization for embedded-software synthesis.

Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004

Input space adaptive design: a high-level methodology for optimizing energy and performance.

Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2004

Common-case computation: a high-level energy and performance optimization technique.

Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Design of high-performance system-on-chips using communication architecture tuners.

Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003

Analysis of power dissipation in embedded systems using real-time operating systems.

Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002

High-level energy macromodeling of embedded software.

Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

High-level test compaction techniques.

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Input Space Adaptive Embedded Software Synthesis.

Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Optimizing public-key encryption for wireless clients.

Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana

Proceedings of the IEEE International Conference on Communications, 2002

2001

TAO: regular expression-based register-transfer level testability analysis and optimization.

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2001

Testing of core-based systems-on-a-chip.

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Accurate Power Macro-modeling Techniques for Complex RTL Circuits.

Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Transient Power Management Through High Level Synthesis.

Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization.

Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 38th Design Automation Conference, 2001

High-level Software Energy Macro-modeling.

Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 38th Design Automation Conference, 2001

LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs.

Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana

Proceedings of the 38th Design Automation Conference, 2001

2000

TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Integrating variable-latency components into high-level synthesis.

Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs.

Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis.

Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha

IEEE Trans. Computers, 2000

High-Level Synthesis with Variable-Latency Components.

Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

: Reducing test application time in high-level test generation.

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips.

Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey

Proceedings of the 37th Conference on Design Automation, 2000

Power analysis of embedded operating systems.

Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha

Proceedings of the 37th Conference on Design Automation, 2000

1999

Power management in high-level synthesis.

Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey

IEEE Trans. Very Large Scale Integr. Syst., 1999

COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems.

Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 1999

Wavesched: a novel scheduling technique for control-flow intensive designs.

Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions.

Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors.

Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

High-level synthesis of low-power control-flow intensive circuits.

Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A framework for testing core-based systems-on-a-chip.

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Memory binding for performance optimization of control-flow intensive behaviors.

Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Common-Case Computation: A High-Level Technique for Power and Performance Optimization.

Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey

Proceedings of the 36th Conference on Design Automation, 1999

1998

A Power Management Methodology for High-Level Synthesis.

Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

TAO: regular expression based high-level testability analysis and optimization.

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Fast high-level power estimation for control-flow intensive design.

Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions.

Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Transforming control-flow intensive designs to facilitate power management.

Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits.

Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 1998 Design, 1998

Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions.

Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha

Proceedings of the 35th Conference on Design Automation, 1998

Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions.

Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 35th Conference on Design Automation, 1998

<i>FACT</i>: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions.

Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 35th Conference on Design Automation, 1998

1997

Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions.

Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

COSYN: Hardware-Software Co-Synthesis of Embedded Systems.

Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha

Proceedings of the 34st Conference on Design Automation, 1997

1996

Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis.

Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha

Proceedings of the Digest of Papers: FTCS-26, 1996