Ganesh C. Patil

According to our database, Ganesh C. Patil authored at least 4 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2019

Si₃N₄: HfO₂ dual-k spacer bulk planar junctionless transistor for mixed signal integrated circuits.

Ramarao Garike, Ganesh C. Patil

IET Circuits Devices Syst., 2019

2013

Engineering buried oxide in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS circuits.

Ganesh C. Patil, Shafi Qureshi

Microelectron. Reliab., 2013

2012

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits.

Ganesh C. Patil, S. Qureshi

Microelectron. J., 2012

2011

Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits.

Ganesh C. Patil, Shafi Qureshi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011