Ganesh Balamurugan

According to our database¹, Ganesh Balamurugan authored at least 38 papers between 1999 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

8-λ × 50 Gbps/λ Heterogeneously Integrated Si-Ph DWDM Transmitter.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, March, 2024

2023

A 256 Gbps Heterogeneously Integrated Silicon Photonic Microring-based DWDM Receiver Suitable for In-Package Optical I/O.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

integrated dual-polarization silicon photonic transceiver with automated polarization control.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

A 3D-integrated 8λ × 32 Gbps λ Silicon Photonic Microring-based DWDM Transmitter.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μA<sub>rms</sub> Input Noise in 22 nm FinFET CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

A 106 Gb/s 2.5 Vppd Linear Microring Modulator Driver with Integrated Photocurrent Sensor in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

2021

A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2021

Silicon Photonic Micro-Ring Modulator-based 4 x 112 Gb/s O-band WDM Transmitter with Ring Photocurrent-based Thermal Control in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

11.6 A 100Gb/s-8.3dBm-Sensitivity PAM-4 Optical Receiver with Integrated TIA, FFE and Direct-Feedback DFE in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A 4×50 Gb/s All-Silicon Ring-based WDM Transceiver with CMOS IC.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Optical Communication, 2021

2020

12.1 A 3D-Integrated Microring-Based 112Gb/s PAM-4 Silicon-Photonic Transmitter with Integrated Nonlinear Equalization and Thermal Control.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

A 112 Gb/s PAM4 Transmitter with Silicon Photonics Microring Modulator and CMOS Driver.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019

56G/112G Link Foundations Standards, Link Budgets & Models.

[BibT_eX]

[DOI]

Ganesh Balamurugan

Ajay Balankutty

Chun-Ming Hsu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

A 112 Gb/s PAM4 Linear TIA with 0.96 pJ/bit Energy Efficiency in 28 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2015

A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the Symposium on VLSI Circuits, 2015

2014

A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2010

A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) reconfigurable transceiver in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008

Joint Equalization and Coding for On-Chip Bus Communication.

[BibT_eX]

[DOI]

Srinivasa R. Sridhara

Ganesh Balamurugan

Naresh R. Shanbhag

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Strong injection locking of low-Q LC oscillators.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

Future Microprocessor Interfaces: Analysis, Design and Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005

8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

2004

Noise-Tolerant Digital System Design

[BibT_eX]

[DOI]

Ganesh Balamurugan

PhD thesis, 2004

2003

Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links.

[BibT_eX]

[DOI]

Ganesh Balamurugan

Naresh R. Shanbhag

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002

A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file.

[BibT_eX]

[DOI]

Krishnamurthy Soumyanath

Shekhar Y. Borkar

IEEE J. Solid State Circuits, 2002

2001

The twin-transistor noise-tolerant dynamic circuit technique.

[BibT_eX]

[DOI]

Ganesh Balamurugan

Naresh R. Shanbhag

IEEE J. Solid State Circuits, 2001

2000

A noise-tolerant dynamic circuit design technique.

[BibT_eX]

[DOI]

Ganesh Balamurugan

Naresh R. Shanbhag

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999

Energy-efficient dynamic circuit design in the presence of crosstalk noise.

[BibT_eX]

[DOI]

Ganesh Balamurugan

Naresh R. Shanbhag

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Ganesh Balamurugan

Timeline

Legend:

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On csauthors.net:

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