Gai Liu

Orcid: 0000-0001-8538-686X

According to our database1, Gai Liu authored at least 22 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Geometric Exterior Elements Calibration of Jilin-1 Linear Array Satellites Based on Star Observation.
Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2023

Linker Code Size Optimization for Native Mobile Applications.
Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction, 2023

2022
FPGA HLS Today: Successes, Challenges, and Opportunities.
ACM Trans. Reconfigurable Technol. Syst., 2022

Linker Code Size Optimization for Native Mobile Applications.
CoRR, 2022

2021
Joint Deep Dictionary Learning.
Proceedings of the Ninth International Conference on Advanced Cloud and Big Data, 2021

2019
PIMap: A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization.
ACM Trans. Reconfigurable Technol. Syst., 2019

Rapid Generation of High-Qality RISC-V Processors from Functional Instruction Set Specifications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips.
IEEE Micro, 2018

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Statistically certified approximate logic synthesis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A Parallel Bandit-Based Approach for Autotuning FPGA Compilation.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Enabling adaptive loop pipelining in high-level synthesis.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Improving high-level synthesis with decoupled data structure optimization.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A reconfigurable analog substrate for highly efficient maximum flow computation.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Architectural Specialization for Inter-Iteration Loop Dependence Patterns.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

CASA: correlation-aware speculative adders.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014


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