Gage Hills

Orcid: 0000-0002-4912-814X

According to our database1, Gage Hills authored at least 25 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Bendable non-silicon RISC-V microprocessor.
Nat., October, 2024

Carbon Connect: An Ecosystem for Sustainable Computing.
CoRR, 2024

2023
Architectural CO<sub>2</sub> Footprint Tool: Designing Sustainable Computer Systems With an Architectural Carbon Modeling Tool.
IEEE Micro, 2023

Design Space Exploration and Optimization for Carbon-Efficient Extended Reality Systems.
CoRR, 2023

Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Carbon-Efficient Design Optimization for Computing Systems.
Proceedings of the 2nd Workshop on Sustainable Computer Systems, 2023

2022
ACT: designing sustainable computer systems with an architectural carbon modeling tool.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021
Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

2020
Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020

2019
The N3XT Approach to Energy-Efficient Abundant-Data Computing.
Proc. IEEE, 2019

SHARC: Self-Healing Analog with RRAM and CNFETs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration.
IEEE J. Solid State Circuits, 2018

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2016
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Transforming nanodevices to next generation nanosystems.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

2015
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x.
Computer, 2015

Time-based sensor interface circuits in carbon nanotube technology.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Multiple Independent Gate FETs: How many gates do we need?
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs.
IEEE J. Solid State Circuits, 2014

Robust design and experimental demonstrations of carbon nanotube digital circuits.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Carbon nanotube circuits: opportunities and challenges.
Proceedings of the Design, Automation and Test in Europe, 2013

Sacha: the Stanford carbon nanotube controlled handshaking robot.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013


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