Gabriele Tombesi

Orcid: 0000-0003-2590-0235

According to our database1, Gabriele Tombesi authored at least 6 papers between 2022 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous Architectures.
CoRR, 2024


2023
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs.
IEEE Des. Test, December, 2023

DECADES: A 67mm<sup>2</sup>, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022


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