Gabriele Minoia

Orcid: 0000-0003-1130-036X

According to our database1, Gabriele Minoia authored at least 11 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

18.4 A 200GS/s 8b 20fJ/c-s Receiver with >60GHz AFE Bandwidth for 800Gb/s Optical Coherent Communications in 5nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

18.3 An 8b 160GS/s 57GHz Bandwidth Time-Interleaved DAC and Driver-Based Transmitter with Adaptive Calibration for 800Gb/s Coherent Optical Applications in 5nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2016
Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures.
IEEE J. Solid State Circuits, 2016

23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A Low-Noise Design Technique for High-Speed CMOS Optical Receivers.
IEEE J. Solid State Circuits, 2014

A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies.
Proceedings of the ESSCIRC 2014, 2014

A 5<sup>th</sup> order gm-C low-pass filter with ±3% cut-off frequency accuracy and 220MHz to 3.3GHz tuning-range in 28nm LP CMOS.
Proceedings of the ESSCIRC 2014, 2014

2012
A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4.
Proceedings of the 38th European Solid-State Circuit conference, 2012


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