Gabriele Bè

Orcid: 0000-0002-4960-6877

According to our database¹, Gabriele Bè authored at least 6 papers between 2022 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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2025

A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, February, 2025

2024

A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023

A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

Concurrent Effect of Redundancy and Switching Algorithms in SAR ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Gabriele Bè

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