Gabriela Nicolescu
Orcid: 0000-0002-5205-9931
According to our database1,
Gabriela Nicolescu
authored at least 130 papers
between 2000 and 2025.
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Bibliography
2025
Int. J. Crit. Infrastructure Prot., 2025
2024
IEEE Trans. Green Commun. Netw., March, 2024
ACM Comput. Surv., February, 2024
Towards Efficient Diagnosis of Performance Bottlenecks in Microservice-Based Applications (Work In Progress paper).
Proceedings of the Companion of the 15th ACM/SPEC International Conference on Performance Engineering, 2024
Natural2CTL: A Dataset for Natural Language Requirements and Their CTL Formal Equivalents.
Proceedings of the Requirements Engineering: Foundation for Software Quality, 2024
Proceedings of the 22nd IEEE Interregional NEWCAS Conference, 2024
2023
Transparent Trace Annotation for Performance Debugging in Microservice-oriented Systems (Work In Progress Paper).
Proceedings of the Companion of the 2023 ACM/SPEC International Conference on Performance Engineering, 2023
Proceedings of the 34th International Workshop on Rapid System Prototyping, 2023
Proceedings of the 34th International Workshop on Rapid System Prototyping, 2023
Proceedings of the 34th International Workshop on Rapid System Prototyping, 2023
Integrated Photonic AI Accelerators Under Hardware Security Attacks: Impacts and Countermeasures.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the International Conference on Machine Learning and Applications, 2023
2022
Proceedings of the 19th Annual International Conference on Privacy, Security & Trust, 2022
Efficient Scheduling, Mapping and Memory Bandwidth Allocation for Safety-Critical Systems.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
2021
Proceedings of the IEEE International Workshop on Rapid System Prototyping, 2021
Proceedings of the Advances in Visual Computing - 16th International Symposium, 2021
2020
Simulator-Based Framework towards Improved Cache Predictability for Multi-Core Avionic Systems.
Proceedings of the Spring Simulation Conference, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
ACM Trans. Embed. Comput. Syst., 2019
2018
Towards Maximum Energy Efficiency in Nanophotonic Interconnects with Thermal-Aware On-Chip Laser Tuning.
IEEE Trans. Emerg. Top. Comput., 2018
ImGA: an improved genetic algorithm for partitioned scheduling on heterogeneous multi-core systems.
Des. Autom. Embed. Syst., 2018
Proceedings of the 50th Computer Simulation Conference, 2018
Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018
DeEPeR: Enhancing Performance and Reliability in Chip-Scale Optical Interconnection Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2017
IEEE Embed. Syst. Lett., 2017
Des. Autom. Embed. Syst., 2017
Proceedings of the International Symposium on Rapid System Prototyping, 2017
Co-design of a low-latency centralized controller for silicon photonic multistage MZI-based switches.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017
2016
J. Supercomput., 2016
Design and Modelling of a Low-Latency Centralized Controller for Optical Integrated Networks.
IEEE Commun. Lett., 2016
Modelling and simulation of optical integrated networks for early-stage design exploration (WIP).
Proceedings of the Summer Computer Simulation Conference, 2016
Proceedings of the Summer Computer Simulation Conference, 2016
Proceedings of the Summer Computer Simulation Conference, 2016
Proceedings of the Summer Computer Simulation Conference, 2016
Cluster-based architecture relying on Optical Integrated Networks with the provision of a low-latency arbiter.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
Proceedings of the 2016 International Symposium on Rapid System Prototyping, 2016
Proceedings of the 2016 IEEE International Conference on Software Quality, 2016
Towards a fast centralized controller for integrated silicon photonic multistage MZI-based switches.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
A generic conceptual framework based on formal representation for the design of continuous/discrete co-simulation tools.
Des. Autom. Embed. Syst., 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Concurr. Comput. Pract. Exp., 2014
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014
Fast and accurate implementation of Canny edge detector on embedded many-core platform.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Efficient transient thermal simulation of 3D ICs with liquid-cooling and through silicon vias.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Reduction methods for adapting optical network on chip topologies to 3D architectures.
Microprocess. Microsystems, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Integrating Memory Optimization with Mapping Algorithms for Multi-Processors System-on-Chip.
ACM Trans. Embed. Comput. Syst., 2012
Softw. Pract. Exp., 2012
J. Electr. Comput. Eng., 2012
Proceedings of the Proceedings Fourth International Symposium on Symbolic Computation in Software Science, 2012
Parallelization strategies of the canny edge detector for multi-core CPUs and many-core GPUs.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012
2011
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method.
ACM J. Emerg. Technol. Comput. Syst., 2011
Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC).
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
A multi-objective decision-theoretic exploration algorithm for platform-based design.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
2010
J. Syst. Archit., 2010
Combining memory optimization with mapping of multimedia applications for multi-processors system-on-chip.
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Computational Analysis, Synthesis, and Design of Dynamic Systems, CRC Press, ISBN: 978-1-420-06784-2, 2010
2009
Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications.
J. Signal Process. Syst., 2009
Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2009
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009
Proceedings of the 2009 Spring Simulation Multiconference, SpringSim 2009, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
Proceedings of the 2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008
2007
J. VLSI Signal Process., 2007
ACM Trans. Design Autom. Electr. Syst., 2007
Generic discrete-continuous simulation model for accurate validation in heterogeneous systems design.
Microelectron. J., 2007
Proceedings of the 2007 Summer Computer Simulation Conference, 2007
Towards the High-Level Design of Optical Networks-on-Chip. Formalization of Opto-Electrical Interfaces.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007
2006
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia.
IEEE Trans. Very Large Scale Integr. Syst., 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006
Formal Definitions of Simulation Interfaces in a Continuous/Discrete Co-Simulation Tool.
Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Survey of Biological High Performance Computing: Algorithms, Implementations and Outlook Research.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
Proceedings of the 2nd IFAC Conference on Analysis and Design of Hybrid Systems, 2006
2005
Proceedings of the Embedded Systems Handbook., 2005
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Discrete-Continuous Simulation Model for Accurate Validation in Component-Based Heterogeneous SoC Design.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
MP SoCs Including Optical Interconnect. Technological Progresses and Challenges for CAD Tools Design.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
2004
Object-based hardware/software component interconnection model for interface design in system-on-a-chip circuits.
J. Syst. Softw., 2004
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004
.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation.
Proceedings of the 2004 Design, 2004
Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
2003
2002
Spécification et validation des systèmes hétérogènes embarqués. (Specification and validation for heterogeneous embedded systems).
PhD thesis, 2002
Tech. Sci. Informatiques, 2002
IEEE Des. Test Comput., 2002
Application of Multi-Domain and Multi-Language Cosimulation to an Optical MEM Switch Design.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
Automatic Generation of Fast Timed Simulation Models for Operating Systems in SoC Design.
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
IEEE Des. Test Comput., 2001
Colif: a Multilevel Design Representation for Application-Specific Multiprocessor System-on-Chip Design.
Proceedings of the 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 2001
Fast timed cosimulation of HW/SW implementation of embedded multiprocessor SoC communication.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
A model for describing communication between aggregate objects in the specification and design of embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
A higher level system communication model for object-oriented specification and design of embedded systems.
Proceedings of ASP-DAC 2001, 2001
Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures.
Proceedings of ASP-DAC 2001, 2001
2000
Des. Autom. Embed. Syst., 2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000