Gabriel Torrens
Orcid: 0000-0002-3676-9992
According to our database1,
Gabriel Torrens
authored at least 25 papers
between 2009 and 2024.
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Bibliography
2024
SRAM-Based PUF Reliability Prediction Using Cell-Imbalance Characterization in the State Space Diagram.
CoRR, 2024
Estimation during Design Phases of Suitable SRAM Cells for PUF Applications Using Separatrix and Mismatch Metrics.
CoRR, 2024
Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment.
CoRR, 2024
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results.
CoRR, 2024
2023
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Selection of SRAM Cells to improve Reliable PUF implementation using Cell Mismatch Metric.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
2019
IEEE Trans. Emerg. Top. Comput., 2019
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019
2017
Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources.
Microelectron. Reliab., 2017
Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
2016
An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies.
Microelectron. Reliab., 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
2014
Microelectron. Reliab., 2014
2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2011
Microelectron. Reliab., 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009