G. Surendra
According to our database1,
G. Surendra
authored at least 10 papers
between 2001 and 2008.
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Bibliography
2008
On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation.
J. Syst. Archit., 2008
2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Instruction Reuse in SPEC, media and packet processing benchmarks: A comparative study of power, performance and related microarchitectural optimizations.
J. Embed. Comput., 2006
2004
On the effectiveness of prefetching and reuse in reducing L1 data cache traffic: a case study of Snort.
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Exploiting program execution phases to trade power and performance for media workload.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications.
Int. J. Parallel Program., 2003
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation.
Proceedings of the 2003 Design, 2003
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation.
Proceedings of the Embedded Software for SoC, 2003
2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001