G. Seetharaman

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2023
Novel fault tolerance topology using corvus seek algorithm for application specific NoC.
Integr., March, 2023

2022
S-shaped and V-shaped binary African vulture optimization algorithm for feature selection.
Expert Syst. J. Knowl. Eng., 2022

2021
Custom NoC topology generation using Discrete Antlion Trapping Mechanism.
Integr., 2021

2018
A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

R3ToS based Partially Reconfigurable Data Flow Pipelined Network on chip.
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay.
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017
Design of R3TOS based reliable low power network on chip.
Proceedings of the Seventh International Conference on Emerging Security Technologies, 2017

Design of reconfigurable and reliable application specific network on chip for R3TOS.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

2014
Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link.
Int. J. Comput. Appl. Technol., 2014

Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link.
J. Electron. Test., 2014

2013
Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links.
Microprocess. Microsystems, 2013

Implementation of One Level 2D DWT Using Multiplier Less Modified Flipping Architecture.
Proceedings of the Asia Modelling Symposium 2013, 2013

ASIC Implementation of One Level 2D-DWT Using Wave-Pipelining.
Proceedings of the Asia Modelling Symposium 2013, 2013

2009
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits.
ACM Trans. Reconfigurable Technol. Syst., 2009

Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

2008
VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme.
VLSI Design, 2008

Automation techniques for implementation of hybrid wave-pipelined 2D DWT.
J. Real Time Image Process., 2008

2007
SOC implementation of wave-pipelined circuits.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007


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