G. Edward Suh
Orcid: 0000-0001-6409-9888Affiliations:
- Cornell University, Ithaca, NY, USA
According to our database1,
G. Edward Suh
authored at least 132 papers
between 2001 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
2024
IEEE Trans. Inf. Theory, May, 2024
Proc. Priv. Enhancing Technol., 2024
Towards Understanding Systems Trade-offs in Retrieval-Augmented Generation Model Inference.
CoRR, 2024
CoRR, 2024
Unlocking Visual Secrets: Inverting Features with Diffusion Priors for Image Reconstruction.
CoRR, 2024
Proceedings of the 33rd USENIX Security Symposium, 2024
Accelerating ReLU for MPC-Based Private Inference with a Communication-Efficient Sign Estimation.
Proceedings of the Seventh Annual Conference on Machine Learning and Systems, 2024
LibPreemptible: Enabling Fast, Adaptive, and Hardware-Assisted User-Space Scheduling.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024
Formal Privacy Proof of Data Encoding: The Possibility and Impossibility of Learnable Encryption.
Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2024
LazyDP: Co-Designing Algorithm-Software for Scalable Training of Differentially Private Recommendation Models.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
2023
CoRR, 2023
Bounding the Invertibility of Privacy-preserving Instance Encoding using Fisher Information.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Cocktail Party Attack: Breaking Aggregation-Based Privacy in Federated Learning Using Independent Component Analysis.
Proceedings of the International Conference on Machine Learning, 2023
Mitigating Metastable Failures in Distributed Systems with Offline Reinforcement Learning.
Proceedings of the First Tiny Papers Track at ICLR 2023, 2023
MACTA: A Multi-agent Reinforcement Learning Approach for Cache Timing Attacks and Detection.
Proceedings of the Eleventh International Conference on Learning Representations, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023
2022
Data Leakage via Access Patterns of Sparse Features in Deep Learning-based Recommendation Systems.
CoRR, 2022
DisaggRec: Architecting Disaggregated Systems for Large-Scale Personalized Recommendation.
CoRR, 2022
STAMP: Lightweight TEE-Assisted MPC for Efficient Privacy-Preserving Machine Learning.
CoRR, 2022
CoRR, 2022
AutoCAT: Reinforcement Learning for Automated Exploration of Cache Timing-Channel Attacks.
CoRR, 2022
Accelerating Path Planning for Autonomous Driving with Hardware-Assisted Memoization.
CoRR, 2022
Proceedings of the PLDI '22: 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation, San Diego, CA, USA, June 13, 2022
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Accelerating Path Planning for Autonomous Driving with Hardware-Assisted Memorization.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022
2021
IACR Cryptol. ePrint Arch., 2021
IEEE Comput. Archit. Lett., 2021
BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Proceedings of the CCS '21: 2021 ACM SIGSAC Conference on Computer and Communications Security, Virtual Event, Republic of Korea, November 15, 2021
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021
BCD deduplication: effective memory compression using partial cache-line deduplication.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021
2020
Path Planning Under Malicious Injections and Removals of Perceived Obstacles: A Probabilistic Programming Approach.
IEEE Robotics Autom. Lett., 2020
MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration.
CoRR, 2020
Proceedings of the 29th USENIX Security Symposium, 2020
Proceedings of the IEEE International Symposium on Information Theory, 2020
Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations.
Proceedings of the 8th International Conference on Learning Representations, 2020
Proceedings of the 8th IEEE Conference on Communications and Network Security, 2020
Efficient nursery sizing for managed languages on multi-core processors with shared caches.
Proceedings of the CGO '20: 18th ACM/IEEE International Symposium on Code Generation and Optimization, 2020
2019
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 32nd IEEE Computer Security Foundations Symposium, 2019
2018
IEEE Comput. Archit. Lett., 2018
Proceedings of the 2018 IEEE Symposium on Security and Privacy, 2018
An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 2018 ACM SIGPLAN International Symposium on Memory Management, 2018
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Reverse engineering convolutional neural networks through side-channel information leaks.
Proceedings of the 55th Annual Design Automation Conference, 2018
Secure Autonomous Cyber-Physical Systems Through Verifiable Information Flow Control.
Proceedings of the 2018 Workshop on Cyber-Physical Systems Security and PrivaCy, 2018
HyperFlow: A Processor Architecture for Nonmalleable, Timing-Safe Information Flow Security.
Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018
2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Verification of a Practical Hardware Security Architecture Through Static Information Flow Analysis.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017
2016
Efficient data supply for hardware accelerators with prefetching and access/execute decoupling.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Lattice priority scheduling: Low-overhead timing-channel protection for a shared memory controller.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 48th International Symposium on Microarchitecture, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Improving worst-case cache performance through selective bypassing and register-indexed cache.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015
2014
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014
Author retrospective for analytical cache models with applications to cache partitioning.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014
Author retrospective AEGIS: architecture for tamper-evident and tamper-resistant processing.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
Low-overhead and high coverage run-time race detection through selective meta-data management.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
2013
IEEE Trans. Computers, 2013
Proceedings of the 2013 IEEE Symposium on Security and Privacy, 2013
Quadrisection-based task mapping on many-core processors for energy-efficient on-chip communication.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
2012
Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints.
Proceedings of the IEEE Symposium on Security and Privacy, 2012
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012
Fast development of hardware-based run-time monitors through architecture framework and high-level synthesis.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
High-performance parallel accelerator for flexible and efficient run-time monitoring.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 46th Annual Conference on Information Sciences and Systems, 2012
Proceedings of the ACM Conference on Computer and Communications Security, 2012
2011
Proceedings of the Trust and Trustworthy Computing - 4th International Conference, 2011
Proceedings of the Trust and Trustworthy Computing - 4th International Conference, 2011
Proceedings of the NOCS 2011, 2011
SRAM-DRAM hybrid memory with applications to efficient register files in fine-grained multi-threading.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable Fabric.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011
2010
Authentication of Processor Hardware Leveraging Performance Limits in Detailed Simulations and Emulations.
Proceedings of the Towards Hardware-Intrinsic Security - Foundations and Practice, 2010
Low power nonvolatile SRAM circuit with integrated low voltage nanocrystal PMOS Flash.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
Implementing dynamic information flow tracking on microprocessors with integrated FPGA fabric (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010
2009
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009
Hardware authentication leveraging performance limits in detailed simulations and emulations.
Proceedings of the 46th Design Automation Conference, 2009
2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Des. Codes Cryptogr., 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the 2005 IEEE Symposium on Security and Privacy (S&P 2005), 2005
Design and Implementation of the AEGIS Single-Chip Secure Processor Using Physical Random Functions.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
2004
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004
2003
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
Proceedings of the 17th Annual International Conference on Supercomputing, 2003
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003
Proceedings of the 40th Design Automation Conference, 2003
Incremental Multiset Hash Functions and Their Application to Memory Integrity Checking.
Proceedings of the Advances in Cryptology - ASIACRYPT 2003, 9th International Conference on the Theory and Application of Cryptology and Information Security, Taipei, Taiwan, November 30, 2003
2002
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002
2001
Proceedings of the Job Scheduling Strategies for Parallel Processing, 2001
Proceedings of the 15th international conference on Supercomputing, 2001