G. Cardoso Medeiros

Orcid: 0000-0002-7480-2474

According to our database1, G. Cardoso Medeiros authored at least 27 papers between 2015 and 2022.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
Defects, Fault Modeling, and Test Development Framework for RRAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022

Hierarchical Memory Diagnosis.
Proceedings of the IEEE European Test Symposium, 2022

PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory.
Proceedings of the IEEE European Test Symposium, 2022

2021
Hard-to-Detect Fault Analysis in FinFET SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Defect and Fault Modeling Framework for STT-MRAM Testing.
IEEE Trans. Emerg. Top. Comput., 2021

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects.
J. Electron. Test., 2021

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs.
Proceedings of the 26th IEEE European Test Symposium, 2021

Intermittent Undefined State Fault in RRAMs.
Proceedings of the 26th IEEE European Test Symposium, 2021

Improving the Detection of Undefined State Faults in FinFET SRAMs.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Modeling Soft-Error Reliability Under Variability.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

2020
Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects.
Proceedings of the IEEE Latin-American Test Symposium, 2020

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects.
J. Electron. Test., 2019

Device-Aware Test: A New Test Approach Towards DPPB Level.
Proceedings of the IEEE International Test Conference, 2019

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing.
Proceedings of the 24th IEEE European Test Symposium, 2019

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs.
Microelectron. Reliab., 2018

A hardware-based approach for SEU monitoring in SRAMs with weak resistive defects.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

2017
Analysing NBTI Impact on SRAMs with Resistive Defects.
J. Electron. Test., 2017

Evaluating the Impact of Resistive Defects on FinFET-Based SRAMs.
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017

Analyzing the behavior of FinFET SRAMs with resistive defects.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

2016
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits.
J. Electron. Test., 2016

NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits' Life Time.
J. Electron. Test., 2016

Analyzing the Impact of SEUs on SRAMs with Resistive-Bridge Defects.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Analyzing NBTI impact on SRAMs with resistive-open defects.
Proceedings of the 17th Latin-American Test Symposium, 2016

2015
NBTI-aware design of integrated circuits: a hardware-based approach.
Proceedings of the 16th Latin-American Test Symposium, 2015


  Loading...