Fumio Murabayashi

According to our database, Fumio Murabayashi authored at least 5 papers between 1989 and 1996.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

1996

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor.

Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto

IEEE J. Solid State Circuits, 1996

1995

A 13.3ns double-precision floating-point ALU and multiplier.

Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

A 120-MHz BiCMOS superscalar RISC processor.

Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura

IEEE J. Solid State Circuits, April, 1994

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor.

Fumio Murabayashi, Takashi Hotta, Shigeya Tanaka, Tatsumi Yamauchi, Hiromichi Yamada, Tetsuo Nakano, Yutaka Kobayashi, Tadaaki Bandoh

IEEE J. Solid State Circuits, March, 1994

1989

A feedback-type BiCMOS logic gate.

Yoji Nishio, Fumio Murabayashi, Shoichi Kotoku, Atsuo Watnabe, Shoji Shukuri, Katsuhiro Shimohigashi

IEEE J. Solid State Circuits, October, 1989