Fumio Arakawa

Orcid: 0000-0002-4129-3554

According to our database1, Fumio Arakawa authored at least 25 papers between 1990 and 2022.

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Bibliography

2022
Special Issue on Cool Chips.
IEEE Micro, 2022

2021
Foreword.
IEICE Trans. Electron., 2021

2018
A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2016
Parallel Design of Feedback Control Systems Utilizing Dead Time for Embedded Multicore Processors.
IEICE Trans. Electron., 2016

2014
Simple One-to-One Architecture for Parallel Execution of Embedded Control Systems.
Proceedings of the 2014 IEEE International Conference on Cyber-Physical Systems, 2014

Parallel design of control systems utilizing dead time for embedded multicore processors.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

Establishing a standard interface between multi-manycore and software tools - SHIM.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

Message from the program committee chairs.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

Panel discussions: Toward wearable computing era, how COOL chip architecture and tools will evolve?
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

2011
Cool Chips.
IEEE Micro, 2011

2009
Guest Editors' Introduction: Cool Chips.
IEEE Micro, 2009

An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU.
Microprocess. Microsystems, 2009

2006
Development of processor cores for digital consumer appliances.
Syst. Comput. Jpn., 2006

SH-X: An embedded processor core for consumer appliances.
J. Embed. Comput., 2006

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core.
IEICE Trans. Electron., 2006

2005
SH-X: an embedded processor core for consumer appliances.
SIGARCH Comput. Archit. News, 2005

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones.
IEICE Trans. Electron., 2005

An Exact Leading Non-Zero Detector for a Floating-Point Unit.
IEICE Trans. Electron., 2005

Low-Power Design of 90-nm SuperH Processor Core.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
Transparent SOC: on-chip analyzing techniques and implementation for embedded processor.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

2000
SH-5: The 64-Bit SuperH Architecture.
IEEE Micro, 2000

1998
SH4 RISC multimedia microprocessor.
IEEE Micro, 1998

1993
The Gmicro/500 superscalar microprocessor with branch buffers.
IEEE Micro, 1993

Design Methodology for GMICRO<sup>TM</sup>/500 TRON Microprocessor.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1990
An analysis of the aliasing probability of multiple-input signature registers in the case of a 2<sup>m</sup>-ary symmetric channel.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990


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