Fuminori Kobayashi

According to our database, Fuminori Kobayashi authored at least 38 papers between 1987 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Analog Correlator by a Dynamically-Reconfigured Switched-Capacitor Circuit.

Fuminori Kobayashi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2016

Direct optical communication on an optically reconfigurable gate array.

Shinya Furukawa, Ili Shairah Abdul Halim, Minoru Watanabe, Fuminori Kobayashi

Proceedings of the Fifth International Conference on Future Communication Technologies, 2016

2015

Integrally accurate resolver-to-digital converter (RDC).

Nordinah Ismail, Fuminori Kobayashi, Manabu Inoue

Proceedings of the 10th Asian Control Conference, 2015

2011

Optically reconflgurable gate array with a polymer-dispersed liquid crystal holographic memory.

Takayuki Mabuchi, Minoru Watanabe, Akifumi Ogiwara, Fuminori Kobayashi

Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

2010

A motor speed control system using a hybrid of dual-loop PLL and feed-forward.

Hidekazu Machida, Michinobu Kambara, Kouta Tanaka, Fuminori Kobayashi

Proceedings of the 11th IEEE International Workshop on Advanced Motion Control, 2010

2009

A PLL configuration for reducing both incoming and inherent jitters.

Fuminori Kobayashi, Yuhta Egashira, Hitoshi Kondoh

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective.

Fuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

Low-jitter PLL by interpolate compensation.

Yutaka Nakanishi, Fuminori Kobayashi, Hitoshi Kondoh

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Holographic memory reconfigurable VLSI.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays.

Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

272 Gate Count Optically Differential Reconfigurable Gate Array VLSI.

Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

An optically differential reconfigurable gate array with a holographic memory.

Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Power consumption advantage of a dynamic optically reconfigurable gate array.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Differential Reconfiguration Architecture suitable for a Holographic Memory.

Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Logic Synthesis and Place-and-Route Environment for ORGAs.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

Optically Reconfigurable Gate Arrays vs. ASICs.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

An Improved Dynamic Optically Reconfigurable Gate Array.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs.

Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A Zero-Overhead Dynamic Optically Reconfigurable Gate Array.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers.

Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004

An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

An optically differential reconfigurable gate array using a 0.18 μm CMOS process.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A High-Density Optically Reconfigurable Gate Array Using Dynamic Method.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the Field Programmable Logic and Application, 2004

Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

Testing Method for Optical Connections Using Gate Array Structure in ORGAs.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003

An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002

An optically differential reconfigurable gate array and its power consumption estimation.

Minoru Watanabe, Fuminori Kobayashi

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

1996

Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's).

Fuminori Kobayashi, Masayuki Haratsu, Masateru Yabumoto, Michio Nakano

IEEE Trans. Ind. Electron., 1996

1995

A Digital PLL with Finite Impulse Responses.

Fuminori Kobayashi, Masayuki Haratsu

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1992

Interpolative variable-speed repetitive control and its application to a deburring robot with cutting load control.

Yoichi Kimura, Ryoji Mukai, Fuminori Kobayashi, Masaru Kobayashi

Adv. Robotics, 1992

1987

Time-varying signals analysis using squared analytic signals.

Fuminori Kobayashi, Hiroshi Suzuki

Proceedings of the IEEE International Conference on Acoustics, 1987