Fulvio Corno

Orcid: 0000-0002-9818-0999

Affiliations:
  • Polytechnic Institute of Turin, Italy


According to our database1, Fulvio Corno authored at least 229 papers between 1992 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Security Evaluation of Arduino Projects Developed by Hobbyist IoT Programmers.
Sensors, March, 2023

How the Preattentive Process is Exploited in Practical Information Visualization Design: A Review.
Int. J. Hum. Comput. Interact., February, 2023

2022
Helping novice developers harness security issues in cloud-IoT systems.
J. Reliab. Intell. Environ., 2022

Computational notebooks to support developers in prototyping IoT systems.
Int. J. Hum. Comput. Stud., 2022

How do end-users program the Internet of Things?
Behav. Inf. Technol., 2022

2021
From Users' Intentions to IF-THEN Rules in the Internet of Things.
ACM Trans. Inf. Syst., 2021

TextCode: A Tool to Support Problem Solving Among Novice Programmers.
Proceedings of the IEEE Symposium on Visual Languages and Human-Centric Computing, 2021

Devices, Information, and People: Abstracting the Internet of Things for End-User Personalization.
Proceedings of the End-User Development - 8th International Symposium, 2021

Perception of Security Issues in the Development of Cloud-IoT Systems by a Novice Programmer.
Proceedings of the Intelligent Environments 2021, 2021

On Computational Notebooks to Empower Physical Computing Novices.
Proceedings of the EICS '21: ACM SIGCHI Symposium on Engineering Interactive Computing Systems, 2021

2020
How is Open Source Software Development Different in Popular IoT Projects?
IEEE Access, 2020

Systematic Variation of Preattentive Attributes to Highlight Relevant Data in Information Visualization.
Proceedings of the 24th International Conference on Information Visualisation, 2020

TAPrec: supporting the composition of trigger-action rules through dynamic recommendations.
Proceedings of the IUI '20: 25th International Conference on Intelligent User Interfaces, 2020

HeyTAP: Bridging the Gaps Between Users' Needs and Technology in IF-THEN Rules via Conversation.
Proceedings of the AVI '20: International Conference on Advanced Visual Interfaces, Island of Ischia, Italy, September 28, 2020

2019
RecRules: Recommending IF-THEN Rules for End-User Development.
ACM Trans. Intell. Syst. Technol., 2019

On the challenges novice programmers experience in developing IoT systems: A Survey.
J. Syst. Softw., 2019

On the impact of dysarthric speech on contemporary ASR cloud platforms.
J. Reliab. Intell. Environ., 2019

Reliability on pervasive well-being: will it soon become a reality? - State of the art and open issues.
J. Reliab. Intell. Environ., 2019

A high-level semantic approach to End-User Development in the Internet of Things.
Int. J. Hum. Comput. Stud., 2019

XDN: cross-device framework for custom notifications management.
Computing, 2019

EUDoptimizer: Assisting End Users in Composing IF-THEN Rules Through Optimization.
IEEE Access, 2019

My IoT Puzzle: Debugging IF-THEN Rules Through the Jigsaw Metaphor.
Proceedings of the End-User Development - 7th International Symposium, 2019

Touch-Based Ontology Browsing on Tablets and Surfaces.
Proceedings of the 43rd IEEE Annual Computer Software and Applications Conference, 2019

Towards Computational Notebooks for IoT Development.
Proceedings of the Extended Abstracts of the 2019 CHI Conference on Human Factors in Computing Systems, 2019

Empowering End Users in Debugging Trigger-Action Rules.
Proceedings of the 2019 CHI Conference on Human Factors in Computing Systems, 2019

2018
User expectations in intelligent environments - Issues and opportunities in the interaction of intelligent users and intelligent environments.
J. Reliab. Intell. Environ., 2018

AwareNotifications: Multi-device semantic notification handling with user-defined preferences.
J. Ambient Intell. Smart Environ., 2018

An Unsupervised and Noninvasive Model for Predicting Network Resource Demands.
IEEE Internet Things J., 2018

"Hey Siri, Do You Understand Me?": Virtual Assistants and Dysarthria.
Proceedings of the Intelligent Environments 2018, 2018

Easing IoT development for novice programmers through code recipes.
Proceedings of the 40th International Conference on Software Engineering: Software Engineering Education and Training, 2018

Collaborative Accessible Gameplay with One-Switch Interfaces.
Proceedings of the IEEE Games, Entertainment, Media Conference, 2018

Message from the ITiP Symposium Chairs.
Proceedings of the 2018 IEEE 42nd Annual Computer Software and Applications Conference, 2018

Assessing Virtual Assistant Capabilities with Italian Dysarthric Speech.
Proceedings of the 20th International ACM SIGACCESS Conference on Computers and Accessibility, 2018

On The Advanced Services That 5G May Provide To IoT Applications.
Proceedings of the IEEE 5G World Forum, 2018

2017
Training Engineers for the Ambient Intelligence Challenge.
IEEE Trans. Educ., 2017

Design and Development of One-Switch Video Games for Children with Severe Motor Disabilities.
ACM Trans. Access. Comput., 2017

A Semantic Web Approach to Simplifying Trigger-Action Programming in the IoT.
Computer, 2017

On the design of an energy and user aware study room.
Proceedings of the 2017 IEEE PES Innovative Smart Grid Technologies Conference Europe, 2017

Pain Points for Novice Programmers of Ambient Intelligence Systems: An Exploratory Study.
Proceedings of the 41st IEEE Annual Computer Software and Applications Conference, 2017

A High-Level Approach Towards End User Development in the IoT.
Proceedings of the 2017 CHI Conference on Human Factors in Computing Systems, 2017

2016
Educating Internet of Things Professionals: The Ambient Intelligence Course.
IT Prof., 2016

Estimate user meaningful places through low-energy mobile sensing.
Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

A Healthcare Support System for Assisted Living Facilities: An IoT Solution.
Proceedings of the 40th IEEE Annual Computer Software and Applications Conference, 2016

Clocks, Bars and Balls: Design and Evaluation of Alternative GNomon Widgets for Children with Disabilities.
Proceedings of the 2016 CHI Conference on Human Factors in Computing Systems, 2016

2015
Supporting caregivers in assisted living facilities for persons with disabilities: a user study.
Univers. Access Inf. Soc., 2015

Playable One-Switch Video Games for Children with Severe Motor Disabilities Based on GNomon.
EAI Endorsed Trans. Serious Games, 2015

Designing for user confidence in intelligent environments.
J. Reliab. Intell. Environ., 2015

Autonomic goal-oriented device management for Smart Environments.
J. Ambient Intell. Smart Environ., 2015

Real-time monitoring of high-level states in smart environments.
J. Ambient Intell. Smart Environ., 2015

Smart Systems.
IT Prof., 2015

A context and user aware smart notification system.
Proceedings of the 2nd IEEE World Forum on Internet of Things, 2015

IoT Meets Exhibition Areas: A Modular Architecture to Improve Proximity Interactions.
Proceedings of the 3rd International Conference on Future Internet of Things and Cloud, 2015

HomeRules: A Tangible End-User Programming Interface for Smart Homes.
Proceedings of the 33rd Annual ACM Conference Extended Abstracts on Human Factors in Computing Systems, 2015

GNomon: Enabling Dynamic One-Switch Games for Children with Severe Motor Disabilities.
Proceedings of the 33rd Annual ACM Conference Extended Abstracts on Human Factors in Computing Systems, 2015

Can We Make Dynamic, Accessible and Fun One-Switch Video Games?
Proceedings of the 17th International ACM SIGACCESS Conference on Computers & Accessibility, 2015

2014
Modeling and formal verification of smart environments.
Secur. Commun. Networks, 2014

Design-time formal verification for smart environments: an exploratory perspective.
J. Ambient Intell. Humaniz. Comput., 2014

SAT based enforcement of domotic effects in smart environments.
J. Ambient Intell. Humaniz. Comput., 2014

JEERP: Energy-Aware Enterprise Resource Planning.
IT Prof., 2014

Advancing Cloud Computing.
IT Prof., 2014

IoT Meets Caregivers: A Healthcare Support System in Assisted Living Facilities.
Proceedings of the Internet of Things. User-Centric IoT, 2014

PowerOnt: An Ontology-Based Approach for Power Consumption Estimation in Smart Homes.
Proceedings of the Internet of Things. User-Centric IoT, 2014

2013
Innovative and Disruptive Technologies [From the Editors].
IT Prof., 2013

Template-Based Ontology Population for Smart Environments Configuration.
Proceedings of the Service-Oriented Computing - ICSOC 2013 Workshops, 2013

The smart home controller on your wrist.
Proceedings of the 2013 ACM International Joint Conference on Pervasive and Ubiquitous Computing, 2013

2012
Intelligent Energy Optimization for User Intelligible Goals in Smart Home Environments.
IEEE Trans. Smart Grid, 2012

Publishing LO(D)D: Linked Open (Dynamic) Data for Smart Sensing and Measuring Environments.
Proceedings of the 3rd International Conference on Ambient Systems, 2012

dWatch: A Personal Wrist Watch for Smart Environments.
Proceedings of the 3rd International Conference on Ambient Systems, 2012

spChains: A Declarative Framework for Data Stream Processing in Pervasive Applications.
Proceedings of the 3rd International Conference on Ambient Systems, 2012

DoMAIns: Domain-based modeling for Ambient Intelligence.
Pervasive Mob. Comput., 2012

2011
What would you ask to your home if it were intelligent? Exploring user expectations about next-generation homes.
J. Ambient Intell. Smart Environ., 2011

DOGeye: Controlling your home with eye interaction.
Interact. Comput., 2011

Design Time Methodology for the Formal Verification of Intelligent Domotic Environments.
Proceedings of the Ambient Intelligence - Software and Applications, 2011

A User-Friendly Interface for Rules Composition in Intelligent Environments.
Proceedings of the Ambient Intelligence - Software and Applications, 2011

Formal Verification of Device State Chart Models.
Proceedings of the 7th International Conference on Intelligent Environments, 2011

2010
Mobile interaction with smart environments through linked data.
Proceedings of the IEEE International Conference on Systems, 2010

DogSim: A state chart simulator for Domotic Environments.
Proceedings of the Eigth Annual IEEE International Conference on Pervasive Computing and Communications, 2010

Eye-based Direct Interaction for Environmental Control in Heterogeneous Smart Environments.
Proceedings of the Handbook of Ambient Intelligence and Smart Environments, 2010

2009
Understanding users and their needs.
Univers. Access Inf. Soc., 2009

A blueprint for integrated eye-controlled environments.
Univers. Access Inf. Soc., 2009

Automatic domotic device interoperation.
IEEE Trans. Consumer Electron., 2009

FaSet: A Set Theory Model for Faceted Search.
Proceedings of the 2009 IEEE/WIC/ACM International Conference on Web Intelligence, 2009

Interoperation Modeling for Intelligent Domotic Environments.
Proceedings of the Ambient Intelligence, 2009

2008
The DOG gateway: enabling ontology-based intelligent domotic environments.
IEEE Trans. Consumer Electron., 2008

Uniform Access to Domotic Environments through Semantics.
Proceedings of the 5th Workshop on Semantic Web Applications and Perspectives (SWAP2008), 2008

DogOnt - Ontology Modeling for Intelligent Domotic Environments.
Proceedings of the Semantic Web - ISWC 2008, 7th International Semantic Web Conference, 2008

DOG: An Ontology-Powered OSGi Domotic Gateway.
Proceedings of the 20th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2008), 2008

Eye Tracking Impact on Quality-of-Life of ALS Patients.
Proceedings of the Computers Helping People with Special Needs, 2008

Integrated speech and gaze control for realistic desktop environments.
Proceedings of the Eye Tracking Research & Application Symposium, 2008

Self-Similarity Metric for Index Pruning in Conceptual Vector Space Models.
Proceedings of the 19th International Workshop on Database and Expert Systems Applications (DEXA 2008), 2008

2007
A reusable 3D visualization component for the semantic web.
Proceedings of the Proceeding of the Twelfth International Conference on 3D Web Technology, 2007

Versatile RDF Representation for Multimedia Semantic Search.
Proceedings of the 19th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2007), 2007

2006
On-the-fly Construction of Web Services Compositions from Natural Language Requests.
J. Softw., 2006

An Extensible Platform for Semantic Classification And Retrieval of Multimedia Resources.
Proceedings of the SWAP 2006, 2006

Domotic house gateway.
Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006

2005
Evolving assembly programs: how games help microprocessor validation.
IEEE Trans. Evol. Comput., 2005

Automatic learning of text-to-concept mappings exploiting WordNet-like lexical networks.
Proceedings of the 2005 ACM Symposium on Applied Computing (SAC), 2005

Composing Web Services on the Basis of Natural Language Requests.
Proceedings of the 2005 IEEE International Conference on Web Services (ICWS 2005), 2005

Specifying Web Service Compositions on the Basis of Natural Language Requests.
Proceedings of the Service-Oriented Computing, 2005

2004
Evolutionary Simulation-Based Validation.
Int. J. Artif. Intell. Tools, 2004

Code Generation for Functional Validation of Pipelined Microprocessors.
J. Electron. Test., 2004

A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
J. Electron. Test., 2004

Automatic Test Program Generation: A Case Study.
IEEE Des. Test Comput., 2004

A multi-level approach to the dependability analysis of networked systems based on the CAN protocol.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Multilingual semantic elaboration in the DOSE platform.
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Impact of Technology on Learning Paradigms and Teaching Practices.
Proceedings of the EDUTECH, 2004

E-learning Issues for Advanced Technical Topics.
Proceedings of the EDUTECH, 2004

Domain Specific Searches Using Conceptual Spectra.
Proceedings of the 16th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2004), 2004

An Agent Based Autonomic Semantic Platform.
Proceedings of the 1st International Conference on Autonomic Computing (ICAC 2004), 2004

Validation of the dependability of CAN-based networked systems.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

On the evolution of corewar warriors.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004

Dynamic optimization of semantic annotation relevance.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004

2003
An Evolutionary Approach to Web Request Prediction.
Proceedings of the Twelfth International World Wide Web Conference - Posters, 2003

A Real-Time Evolutionary Algorithm for Web Prediction.
Proceedings of the 2003 IEEE / WIC International Conference on Web Intelligence, 2003

Automatic Test Program Generation for Pipeline Processors.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

DOSE: A Distributed Open Semantic Elaboration Platform.
Proceedings of the 15th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2003), 2003

Exploiting Auto-adaptive 7GP for Highly Effective Test Programs Generation.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2003

Relating vehicle-level and network-level reliability through high-level fault injection.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

An Enhanced Framework for Microprocessor Test-Program Generation.
Proceedings of the Genetic Programming, 6th European Conference, EuroGP 2003, 2003

Code generation for functional validation of pipelined microprocessors.
Proceedings of the 8th European Test Workshop, 2003

System-Level Analysis of Fault Effects in an Automotive Environment.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Fully Automatic Test Program Generation for Microprocessor Cores.
Proceedings of the 2003 Design, 2003

Exploiting co-evolution and a modified island model to climb the Core War hill.
Proceedings of the IEEE Congress on Evolutionary Computation, 2003

Dynamic prediction of Web requests.
Proceedings of the IEEE Congress on Evolutionary Computation, 2003

2002
Initializability analysis of synchronous sequential circuits.
ACM Trans. Design Autom. Electr. Syst., 2002

An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Reducing Test Application Time through Interleaved Scan.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

An evolutionary algorithm for reducing integrated-circuit test application time.
Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), 2002

A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Automatic Test Program Generation from RT-Level Microprocessor Descriptions.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Analysis of the Equivalences and Dominances of Transient Faults at the RT Level.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

A cost-effective solution for eye-gaze assistive technology.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

Hypervideo: A Parameterized Hotspot Approach.
Proceedings of the IADIS International Conference WWW/Internet 2002, 2002

Evolutionary Techniques for Minimizing Test Signals Application Time.
Proceedings of the Applications of Evolutionary Computing, 2002

New Techniques for Speeding-Up Fault-Injection Campaigns.
Proceedings of the 2002 Design, 2002

Efficient machine-code test-program induction.
Proceedings of the 2002 Congress on Evolutionary Computation, 2002

Evolutionary Test Program Induction for Microprocessor Design Verification.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Interactive Visit of a Website.
Proceedings of WebNet 2001, 2001

Evolving effective CA/CSTP: BIST architectures for sequential circuits.
Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), 2001

ARPIA: A High-Level Evolutionary Test Signal Generator.
Proceedings of the Applications of Evolutionary Computing, 2001

On the test of microprocessor IP cores.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Effective Techniques for High-Level ATPG.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
RT-Level ITC'99 Benchmarks and First ATPG Results.
IEEE Des. Test Comput., 2000

An Intelligent User Interface oriented to non-expert users.
Proceedings of WebNet 2000 - World Conference on the WWW and Internet, San Antonio, Texas, USA, October 30, 2000

Enhancing Interactivity for Self-Evaluation in XML-based Courseware.
Proceedings of WebNet 2000 - World Conference on the WWW and Internet, San Antonio, Texas, USA, October 30, 2000

High-Level Observability for Effective High-Level ATPG.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Low Power BIST via Non-Linear Hybrid Cellular Automata.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

An improved cellular automata-based BIST architecture for sequential circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata.
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

A genetic algorithm-based system for generating test programs for microprocessor IP cores.
Proceedings of the 12th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2000), 2000

Evolving Cellular Automata for Self-Testing Hardware.
Proceedings of the Evolvable Systems: From Biology to Hardware, 2000

An RT-level fault model with high gate level correlation.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Automatic Validation of Protocol Interfaces Described in VHDL.
Proceedings of the Real-World Applications of Evolutionary Computing, 2000

Prediction of Power Requirements for High-Speed Circuits.
Proceedings of the Real-World Applications of Evolutionary Computing, 2000

CA-CSTP: a new BIST architecture for sequential circuits.
Proceedings of the 5th European Test Workshop, 2000

Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience.
Proceedings of the 2000 Design, 2000

Exploiting the Selfish Gene algorithm for evolving hardware cellular automata.
Proceedings of the 2000 Congress on Evolutionary Computation, 2000

1999
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Exploiting Behavioral Information in Gate-Level ATPG.
J. Electron. Test., 1999

RT-level TPG Exploiting High-Level Synthesis Information.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Simulation-based sequential equivalence checking of RTL VHDL.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

ALPS: A Peak Power Estimation Tool for Sequential Circuits.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms.
Proceedings of the Evolutionary Image Analysis, 1999

Test Pattern Generation Under Low Power Constraints.
Proceedings of the Evolutionary Image Analysis, 1999

A new BIST architecture for low power circuits.
Proceedings of the 4th European Test Workshop, 1999

Optimal Vector Selection for Low Power BIST.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization.
Proceedings of the 1999 Design, 1999

Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms.
Proceedings of the 1999 Design, 1999

Optimizing deceptive functions with the SG-Clans algorithm.
Proceedings of the 1999 Congress on Evolutionary Computation, 1999

Verifying the equivalence of sequential circuits with genetic algorithms.
Proceedings of the 1999 Congress on Evolutionary Computation, 1999

1998
The General Product Machine: a New Model for Symbolic FSM Traversal.
Formal Methods Syst. Des., 1998

Integrating Online and Offline Testing of a Switching Memory.
IEEE Des. Test Comput., 1998

A Test Pattern Generation Methodology for Low-Power Consumption.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

The selfish gene algorithm: a new evolutionary optimization strategy.
Proceedings of the 1998 ACM symposium on Applied Computing, 1998

VEGA: a verification tool based on genetic algorithms.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Enhancing topological ATPG with high-level information and symbolic techniques.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

A System for Evaluating On-Line Testability at the RT-level.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques.
Proceedings of the 1998 Design, 1998

Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection.
Proceedings of the 1998 Design, 1998

A Test Pattern Generation Algorithm Exploiting Behavioral Information.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Cellular automata for deterministic sequential test pattern generation.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

SAARA: a simulated annealing algorithm for test pattern generation for digital circuits.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997

Testability Analysis and ATPG on Behavioral RT-Level VHDL.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization.
Proceedings of the 9th International Conference on Tools with Artificial Intelligence, 1997

GA-Based Performance Analysis of Network Protocols.
Proceedings of the 9th International Conference on Tools with Artificial Intelligence, 1997

A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Boolean Function Manipulation on a Parallel System Using BDDs.
Proceedings of the High-Performance Computing and Networking, 1997

New static compaction techniques of test sequences for sequential circuits.
Proceedings of the European Design and Test Conference, 1997

Hybrid symbolic-explicit techniques for the graph coloring problem.
Proceedings of the European Design and Test Conference, 1997

Simulation-based verification of network protocols performance.
Proceedings of the Advances in Hardware Design and Verification, 1997

Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Guaranteeing Testability in Re-encoding for Low Power.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Circular Self-Test Path for FSMs.
IEEE Des. Test Comput., 1996

Scan insertion criteria for low design impact.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits.
Proceedings of the Parallel Problem Solving from Nature, 1996

Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits.
Proceedings of the Eigth International Conference on Tools with Artificial Intelligence, 1996

A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits.
Proceedings of the High-Performance Computing and Networking, 1996

Fault tolerant and BIST design of a FIFO cell.
Proceedings of the conference on European design automation, 1996

Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment.
Proceedings of the conference on European design automation, 1996

On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications.
Proceedings of the Dependable Computing, 1996

Advanced Techniques for GA-based sequential ATPGs.
Proceedings of the 1996 European Design and Test Conference, 1996

Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
A portable ATPG tool for parallel and distributed systems.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Improving topological ATPG with symbolic techniques.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Testing a Switching Memory in a Telcommunication System.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

A PVM tool for automatic test generation on parallel and distributed systems.
Proceedings of the High-Performance Computing and Networking, 1995

GARDA: a diagnostic ATPG for large synchronous sequential circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

Using symbolic techniques to find the maximum clique in very large sparse graphs.
Proceedings of the 1995 European Design and Test Conference, 1995

Proving testing preorders for process algebra descriptions.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
A new functional fault model for system-level descriptions.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Making the Circular Self-Test Path Technique Effective for Real Circuits.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

An experimental analysis of the effectiveness of the circular self-test path technique.
Proceedings of the Proceedings EURO-DAC'94, 1994

System-Level Modeling and Verification: a Comprehensive Design Methodology.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

A process algebra interpretation of a verification oriented overlanguage of VHDL.
Proceedings of the Proceedings EURO-DAC'94, 1994

1993
An approach to sequential circuit diagnosis based on formal verification techniques.
J. Electron. Test., 1993

An efficient tool for system-level verification of behaviors and temporal properties.
Proceedings of the European Design Automation Conference 1993, 1993

Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

A Methodology for System-Level Design for Verifiability.
Proceedings of the Correct Hardware Design and Verification Methods, 1993

1992
A simulation-based approach to test pattern generation for synchronous sequential circuits.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Sequential Circuit Diagnosis Based on Formal Verification Techniques.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Cross-fertilizing FSM verification techniques and sequential diagnosis.
Proceedings of the conference on European design automation, 1992

A New Model for Improving symbolic Product Machine Traversal.
Proceedings of the 29th Design Automation Conference, 1992


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