Fule Li

Orcid: 0000-0002-7341-7240

According to our database¹, Fule Li authored at least 71 papers between 2006 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2024

A 14-Bit 4 GS/s Two-Way Interleaved Pipelined ADC With Aperture Error Tunning.

[BibT_eX]

[DOI]

Peilin Yang

Fule Li

Zhihua Wang

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

Corrigendum to 'Distributed sliding mode control for a class of impulsive uncertain delayed partial differential equations via sliding mode compensator approach' [European Journal of Control 77 (2024) 100984].

[BibT_eX]

[DOI]

Eur. J. Control, 2024

Distributed sliding mode control for a class of impulsive uncertain delayed partial differential equations via sliding mode compensator approach.

[BibT_eX]

[DOI]

Eur. J. Control, 2024

A High Linearity ADC Front-End Circuit for Single-Ended Inputs.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

A 3-MHz-3-GHz 8-Phase Reset-Free Anti-Harmonic Delay-Locked Loop Using Phase Difference Composition in 65-nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

A Floating-Ring Hybrid Amplifier Insensitive to PVT and Common-mode Variation without CMFB for High-Speed ADCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A Reconfigurable Continuous-Time Delta-Sigma Modulator Structure Using Hybrid Loop Filter and Time-Interleaved Quantizer.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

A Low Noise High Speed Dynamic Comparator Insensitive to PVT and Common-mode Input.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A Wide Input Common-mode Range Pipelined ADC Front-end with Common-mode Refreshing.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

All-Digital Background Calibration of a Pipelined-SAR ADC Using the "Split ADC" Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Current-Steering DAC Calibration Using Q-Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

High Linearity Front-End Circuit for RF Sampling ADCs with Nonlinear Junction Capacitor Cancellation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Self-Regulating Negative Charge Pump Using Multi-Phase Clock for Wideband ADCs.

[BibT_eX]

[DOI]

Haoran Wang

Junjie Jing

Fule Li

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A statistics-based background capacitor mismatch calibration algorithm for SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021

A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

A 12-Bit 2-GS/s Pipelined ADC Front-End Stage with Aperture Error Tuning and Split MDAC.

[BibT_eX]

[DOI]

Peilin Yang

Fule Li

Zhihua Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 12-bit 800MS/s pipelined A/D converter.

[BibT_eX]

[DOI]

Haoran Wang

Fule Li

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs.

[BibT_eX]

[DOI]

Xiao Wang

Fule Li

Zhihua Wang

IEEE Trans. Circuits Syst., 2020

A 530 nA quiescent current low-dropout regulator with embedded reference for wake-up receivers.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2020

A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019

A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

DCO gain calibration technique in fractional-N Δ-Σ PLL based two-point phase modulators.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018

400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Low-Power 12-bit 2GS/s Time-Interleaved Pipelined-SAR ADC in 28nm CMOS Process.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 14-bit 250MS/s Low-Power Pipeline ADC with Aperture Error Eliminating Technique.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

A Wireless Body Sound Sensor with a Dedicated Compact Chipset.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2017

A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

A low-offset dynamic comparator with input offset-cancellation.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A 14bit 320MS/s pipelined-SAR ADC based on multiplexing of dynamic amplifier.

[BibT_eX]

[DOI]

Honghao Chu

Fule Li

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

High speed serial interface transceiver controller based on JESD204B.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

An 11-bit 200MS/s subrange SAR ADC with charge-compensation-based reference buffer.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Aperture error reduction technique for subrange SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs.

[BibT_eX]

[DOI]

Xiao Wang

Fule Li

Zhihua Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A Low-Cost UHF RFID System With OCA Tag for Short-Range Communication.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Electron., 2015

A power-efficient reference buffer with wide swing for switched-capacitor ADC.

[BibT_eX]

[DOI]

Microelectron. J., 2015

A power-efficient 14-bit 250MS/s pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A digital blind background calibration algorithm for pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A 14-bit 200MS/s low-power pipelined flash-SAR ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Charge-compensation-based reference technique for switched-capacitor ADCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

Dedicated ICs for wearable body sound monitoring.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A calibration technique for SAR ADC based on code density test.

[BibT_eX]

[DOI]

Xian Gu

XiuJu He

Fule Li

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

A low-power DC offset calibration method independent of IF gain for zero-IF receiver.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2014

2013

A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

Lifetime tracing of cardiopulmonary sounds with ultra-low-power sound sensor stick connected to wireless mobile network.

[BibT_eX]

[DOI]

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

An efficient calibration technique for pipeline ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A LUT-free DC offset calibration method for removing the PGA-gain-correlated offset residue.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A merged first and second stage for low power pipelined ADC.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 14-bit pipelined ADC with digital background nonlinearity calibration.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

A current-to-voltage integrator using area-efficient correlated double sampling technique.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 12-bit, 270MS/s pipelined ADC with SHA-eliminating front end.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2010

An energy-efficient SoC for closed-loop medical monitoring and intervention.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Robust Radio Frequency Identification System Enhanced with Spread Spectrum Technique.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

A 12-bit 3.7-Msample/s Pipelined A/D Converter Based on the Novel Capacitor Mismatch Calibration Technique.

[BibT_eX]

[DOI]

Shuaiqi Wang

Fule Li

Yasuaki Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007

An Incomplete Settling Technique for Pipelined Analog-to-Digital Converters.

[BibT_eX]

[DOI]

Fule Li

Zhihua Wang

Dongmei Li

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Pipelined A/D Conversion Technique with Low INL and DNL.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

A 15-bit 10-Msample/s Pipelined A/D Converter Based on Incomplete Settling Principle.

[BibT_eX]

[DOI]

Shuaiqi Wang

Fule Li

Yasuaki Inoue

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Fule Li

Timeline

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