A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power. - Fujun Bai; Baoyu Xiong; Xiaofei Xue; Weizhe Song; Baofeng Wu; Ni Fu; Bing Yu; Huifu Duan; Xiaowei Han; Alessandro Minzoni; Qiwei Ren (ASICON, 2017)

Semantic Segmentation of Panoramic Images for Real-Time Parking Slot Detection. - Cong Lai; Qingyu Yang; Yixin Guo; Fujun Bai; Hongbin Sun 001 (Remote. Sens., 2022)

A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV. - Song Wang; Bing Yu; Wenwu Xiao; Fujun Bai; Xiaodong Long; Liang Bai; Xuerong Jia; Fengguo Zuo; Jie Tan; Yixin Guo; Peng Sun; Jun Zhou; et al. (VLSI Technology and Circuits, 2023)

A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder. - Fujun Bai; Song Wang; Xuerong Jia; Yixin Guo; Bing Yu; Hang Wang; Cong Lai; Qiwei Ren; Hongbin Sun 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Hf0.5Zr0.5O2 1T-1C FeRAM arrays with excellent endurance performance for embedded memory. - Wenwu Xiao; Yue Peng; Yan Liu; Huifu Duan; Fujun Bai; Bing Yu; Qiwei Ren; Xiao Yu; Genquan Han (Sci. China Inf. Sci., 2023)