Fujio Masuoka

According to our database, Fujio Masuoka authored at least 11 papers between 1989 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.

Yisuo Li, Ken'ichi Kanazawa, Tetsuo Izawa, Koji Sakui, Georg Strof, Oskar Baumgartner, Gerhard Rzepa, Markus Karner, Zlatan Stanojevic, Nozomu Harada, Fujio Masuoka

Proceedings of the IEEE International Memory Workshop, 2021

2008

A New Architecture for High-Density High-Performance SGT <i>nor</i> Flash Memory.

Takuya Kadowaki, Yoshizumi Yamakawa, Hiroki Nakamura, Yasuo Kimura, Michio Niwano, Fujio Masuoka

IEEE Trans. Circuits Syst. II Express Briefs, 2008

2006

Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering.

Yasue Yamamoto, Takeshi Hidaka, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka

IEICE Trans. Electron., 2006

2001

0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation.

Akira Tanabe, Masato Umetani, Ikuo Fujiwara, Takayuki Ogura, Kotaro Kataoka, Masao Okihara, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka

IEEE J. Solid State Circuits, 2001

An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current.

Tetsuo Endoh, Kazuhisa Sunaga, Hiroshi Sakuraba, Fujio Masuoka

IEEE J. Solid State Circuits, 2001

An on-chip 96.5% current efficiency CMOS linear regulator.

Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka

Proceedings of ASP-DAC 2001, 2001

1999

New three-dimensional memory array architecture for future ultrahigh-density DRAM.

Tetsuo Endoh, Katsuhisa Shinmei, Hiroshi Sakuraba, Fujio Masuoka

IEEE J. Solid State Circuits, 1999

1995

A 2/3-in 2 million pixel STACK-CCD HDTV imager.

Hirofumi Yamashita, Michio Sasaki, Shinji Ohsawa, Ryohei Miyagawa, Eiji Ohba, Keiji Mabuchi, Nobuo Nakamura, Nagataka Tanaka, Nahoko Endoh, Ikuko Inoue, Yoshiyuki Matsunaga, Yoshitaka Egawa, Yukio Endo, Tetsuya Yamaguchi, Yoshinori Iida, Akihiko Furukawa, Sohei Manabe, Yoshiki Ishizuka, Hideo Ichinose, Takako Niiyama, Hisanori Ihara, Hidetoshi Nozaki, Isamu Yanase, Naoshi Sakuma, Takeo Sakakubo, Hiroki Honda, Fujio Masuoka, Okio Yoshida, Hiroyuki Tango, Shun-ichi Sano

IEEE J. Solid State Circuits, August, 1995

1994

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory.

Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara

IEEE J. Solid State Circuits, November, 1994

1993

Reliability issues of flash memory cells.

Seiichi Aritome, Riichiro Shirota, Gertjan Hemink, Tetsuo Endoh, Fujio Masuoka

Proc. IEEE, 1993

1989

An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode.

Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka

IEEE J. Solid State Circuits, June, 1989