Freeman Zhong
According to our database1,
Freeman Zhong
authored at least 8 papers
between 2005 and 2014.
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Bibliography
2014
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS.
IEEE J. Solid State Circuits, 2014
2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
A self-calibrating multi-VCO PLL scheme with leakage and capacitive modulation mitigations.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2011
A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS.
IEEE J. Solid State Circuits, 2011
A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2005
A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization.
IEEE J. Solid State Circuits, 2005