Fredrik Dahlgren

According to our database, Fredrik Dahlgren authored at least 38 papers between 1991 and 2015.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2015

HyComp: a hybrid cache compression method for selection of data-type-specific compression methods.

Angelos Arelakis, Fredrik Dahlgren, Per Stenström

Proceedings of the 48th International Symposium on Microarchitecture, 2015

2007

Partial Continuous Functions and Admissible Domain Representations.

Fredrik Dahlgren

J. Log. Comput., 2007

2004

Computability and continuity in metric partial algebras equipped with computability structures.

Fredrik Dahlgren

Math. Log. Q., 2004

2002

TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors.

Magnus Ekman, Per Stenström, Fredrik Dahlgren

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

2001

Future Mobile Phones - Complex Design Challenges from an Embedded Systems Perspective.

Fredrik Dahlgren

Proceedings of the 7th International Conference on Engineering of Complex Computer Systems (ICECCS 2001), 2001

Topic 08+13: Instruction-Level Parallelism and Computer Architecture.

Eduard Ayguadé, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, André Seznec

Proceedings of the Euro-Par 2001: Parallel Processing, 2001

2000

Recency-based TLB preloading.

Ashley Saulsbury, Fredrik Dahlgren, Per Stenström

Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Reducing Ownership Overhead for Load-Store Sequences in Cache-Coherent Multiprocessors.

Jim Nilsson, Fredrik Dahlgren

Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Exploration of the Spatial Locality on Emerging Applications and the Consequences for Cache Performance.

Martin Kämpe, Fredrik Dahlgren

Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

A Prefetching Technique for Irregular Accesses to Linked Data Structures.

Magnus Karlsson, Fredrik Dahlgren, Per Stenström

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1999

Evaluation of Compiler-Controlled Updating to Reduce Coherence-Miss Penalties in Shared-Memory Multiprocessors.

Jonas Skeppstedt, Fredrik Dahlgren, Per Stenström

J. Parallel Distributed Comput., 1999

Techniques for Improving Performance of Hybrid Snooping Cache Protocols.

Fredrik Dahlgren

J. Parallel Distributed Comput., 1999

Cache-Only Memory Architectures.

Fredrik Dahlgren, Josep Torrellas

Computer, 1999

Efficient management of memory hierarchies in embedded DRAM systems.

Ashley Saulsbury, Su-Jaen Huang, Fredrik Dahlgren

Proceedings of the 13th international conference on Supercomputing, 1999

Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors.

Jim Nilsson, Fredrik Dahlgren

Proceedings of the International Conference on Parallel Processing 1999, 1999

1998

Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors.

Fredrik Dahlgren, Michel Dubois, Per Stenström

IEEE Trans. Computers, 1998

An evaluation of hardware-based and compiler-controlled optimizations of snooping cache protocols.

Fredrik Dahlgren, Jonas Skeppstedt, Per Stenström

Future Gener. Comput. Syst., 1998

A holistic approach to computer system design education based on system simulation techniques.

Per Stenström, Fredrik Dahlgren

Proceedings of the 1998 workshop on Computer architecture education, 1998

SimICS/Sun4m: A Virtual Workstation.

Peter S. Magnusson, Fredrik Larsson, Andreas Moestedt, Bengt Werner, Jim Nilsson, Per Stenström, Fredrik Lundholm, Magnus Karlsson, Fredrik Dahlgren, Håkan Grahn

Proceedings of the 1998 USENIX Annual Technical Conference, 1998

The Sensitivity of Communication Mechanisms to Bandwidth and Latency.

Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz, Anant Agarwal

Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

1997

Boosting the Performance of Shared Memory Multiprocessors.

Per Stenström, Mats Brorsson, Fredrik Dahlgren, Håkan Grahn, Michel Dubois

Computer, 1997

Reducing the Read-Miss Penalty for Flat COMA Protocols.

Fredrik Dahlgren, Per Stenström, Mårten Björkman

Comput. J., 1997

Reducing the Replacement Overhead in Bus-Based COMA Multiprocessors.

Fredrik Dahlgren, Anders Landin

Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

1996

Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors.

Fredrik Dahlgren, Per Stenström

IEEE Trans. Parallel Distributed Syst., 1996

Applications for Shared Memory Multiprocessors (Guest Editors' Introduction).

Per Stenström, Fredrik Dahlgren

Computer, 1996

Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors.

Anders Landin, Fredrik Dahlgren

Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

1995

Sequential Hardware Prefetching in Shared-Memory Multiprocessors.

Fredrik Dahlgren, Michel Dubois, Per Stenström

IEEE Trans. Parallel Distributed Syst., 1995

Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors.

Fredrik Dahlgren, Per Stenström

J. Parallel Distributed Comput., 1995

Boosting the Performance of Hybrid Snooping Cache Protocols.

Fredrik Dahlgren

Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors.

Fredrik Dahlgren, Per Stenström

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

Using hints to reduce the read miss penalty for flat COMA protocols.

Mårten Björkman, Fredrik Dahlgren, Per Stenström

Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994

Combined Performance Gains of Simple Cache Protocol Extensions.

Fredrik Dahlgren, Michel Dubois, Per Stenström

Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

Reducing the Write Traffic for a Hybrid Cache Protocol.

Fredrik Dahlgren, Per Stenström

Proceedings of the 1994 International Conference on Parallel Processing, 1994

1993

Fixed and Adaptive Sequential Prefetching in Shared Memory Multiprocessors.

Fredrik Dahlgren, Michel Dubois, Per Stenström

Proceedings of the 1993 International Conference on Parallel Processing, 1993

The Cachemire Test Bench A Flexible And Effective Approach For Simulation Of Multiprocessors.

Mats Brorsson, Fredrik Dahlgren, Håkan Nilsson, Per Stenström

Proceedings of the Proceedings 26th Annual Simulation Symposium, ANSS 1993, 1993

1991

On Reconfigurable On-Chip Data Caches.

Fredrik Dahlgren, Per Stenström

Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

A Lockup-Free Multiprocessor Cache Design.

Per Stenström, Fredrik Dahlgren, Lars Lundberg

Proceedings of the International Conference on Parallel Processing, 1991

A program-driven simulation model of an MIMD multiprocessor.

Fredrik Dahlgren

Proceedings of the Proceedings 24th Annual Simulation Symposium (ANSS-24 1991), 1991