Frédéric Mallet

Orcid: 0000-0002-9088-9821

Affiliations:
  • Université Nice Sophia Antipolis, France
  • INRIA Sophia Antipolis Méditerranée; France


According to our database1, Frédéric Mallet authored at least 104 papers between 1998 and 2024.

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Bibliography

2024
A Scalable Approach to Detecting Safety Requirements Inconsistencies for Railway Systems.
IEEE Trans. Intell. Transp. Syst., August, 2024

Specification and Verification of Multi-Clock Systems Using a Temporal Logic with Clock Constraints.
Formal Aspects Comput., June, 2024

Real-Time CCSL: Application to the Mechanical Lung Ventilator.
Proceedings of the Rigorous State-Based Methods - 10th International Conference, 2024

Spatio-Temporal Framework for Verifying Safety Rules in Autonomous Vehicles.
Proceedings of the ACM/IEEE 27th International Conference on Model Driven Engineering Languages and Systems, 2024

2023
Automated Synthesis of Safe Timing Behaviors for Requirements Models Using CCSL.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Accelerating Reinforcement Learning-Based CCSL Specification Synthesis Using Curiosity-Driven Exploration.
IEEE Trans. Computers, May, 2023

Time: It is only Logical!
Proceedings of the Theories of Programming and Formal Methods, 2023

2022
Formally verifying consistency of sequence diagrams for safety critical systems.
Sci. Comput. Program., 2022

A dynamic logic for verification of synchronous models based on theorem proving.
Frontiers Comput. Sci., 2022

2021
A clock-based dynamic logic for the verification of CCSL specifications in synchronous systems.
Sci. Comput. Program., 2021

A clock-based dynamic logic for schedulability analysis of CCSL specifications.
Sci. Comput. Program., 2021

Preface - FTSCS 2019.
Sci. Comput. Program., 2021

Enumeration and Deduction Driven Co-Synthesis of CCSL Specifications using Reinforcement Learning.
Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

EPSAAV: An Extensible Platform for Safety Analysis of Autonomous Vehicles.
Proceedings of the Advances in Model and Data Engineering in the Digitalization Era, 2021

Model-driven approach for the design of Multi-Chain Smart Contracts.
Proceedings of the 3rd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2021

2020
Editorial - Theoretical Aspects of Software Engineering (2017).
Sci. Comput. Program., 2020

A verification framework for spatio-temporal consistency language with CCSL as a specification language.
Frontiers Comput. Sci., 2020

TRAP: trace runtime analysis of properties.
Frontiers Comput. Sci., 2020

Formally Verifying Sequence Diagrams for Safety Critical Systems.
Proceedings of the International Symposium on Theoretical Aspects of Software Engineering, 2020

Modeling and Verifying Uncertainty-Aware Timing Behaviors using Parametric Logical Time Constraint.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
A framework to specify system requirements using natural interpretation of UML/MARTE diagrams.
Softw. Syst. Model., 2019

A Logical Approach for the Schedulability Analysis of CCSL.
Proceedings of the 2019 International Symposium on Theoretical Aspects of Software Engineering, 2019

A Model-Based Combination Language for Scheduling Verification.
Proceedings of the Model-Driven Engineering and Software Development, 2019

Meta-models Combination for Reusing Verification Techniques.
Proceedings of the 7th International Conference on Model-Driven Engineering and Software Development, 2019

SMT-Based Bounded Schedulability Analysis of the Clock Constraint Specification Language.
Proceedings of the Fundamental Approaches to Software Engineering, 2019

Sample-Guided Automated Synthesis for CCSL Specifications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Language-Based Multi-View Approach for Combining Functional and Security Models.
Proceedings of the 26th Asia-Pacific Software Engineering Conference, 2019

2018
Periodic scheduling for MARTE/CCSL: Theory and practice.
Sci. Comput. Program., 2018

pCSSL: A stochastic extension to MARTE/CCSL for modeling uncertainty in Cyber Physical Systems.
Sci. Comput. Program., 2018

Work-in-Progress: From Logical Time Scheduling to Real-Time Scheduling.
Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

Embedding CCSL into Dynamic Logic: A Logical Approach for the Verification of CCSL Specifications.
Proceedings of the Formal Techniques for Safety-Critical Systems, 2018

Time in SCCharts.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

xSHS: An Executable Domain-Specific Modeling Language for Modeling Stochastic and Hybrid Behaviors of Cyber-Physical Systems.
Proceedings of the 25th Asia-Pacific Software Engineering Conference, 2018

2017
Quantitative Performance Evaluation of Uncertainty-Aware Hybrid AADL Designs Using Statistical Model Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Explicit Control of Dataflow Graphs with MARTE/CCSL.
Proceedings of the 5th International Conference on Model-Driven Engineering and Software Development, 2017

2016
Natural interpretation of UML/MARTE diagrams for system requirements specification.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

An SMT-Based Approach to the Formal Analysis of MARTE/CCSL.
Proceedings of the Formal Methods and Software Engineering, 2016

Flexible runtime verification based on logical clock constraints.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

MARTE/pCCSL: Modeling and Refining Stochastic Behaviors of CPSs with Probabilistic Logical Clocks.
Proceedings of the Formal Aspects of Component Software - 13th International Conference, 2016

2015
Correctness issues on MARTE/CCSL constraints.
Sci. Comput. Program., 2015

Progressive and explicit refinement of scheduling for multidimensional data-flow applications using UML MARTE.
Des. Autom. Embed. Syst., 2015

MARTE/CCSL for Modeling Cyber-Physical Systems.
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

A Model-Driven Based Environment for Automatic Model Coordination.
Proceedings of the MoDELS 2015 Demo and Poster Session co-located with ACM/IEEE 18th International Conference on Model Driven Engineering Languages and Systems (MoDELS 2015), 2015

A Behavioral Coordination Operator Language (BCOoL).
Proceedings of the 18th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems, 2015

An Executable Semantics of Clock Constraint Specification Language and Its Applications.
Proceedings of the Formal Techniques for Safety-Critical Systems, 2015

2014
Timed Automata Semantics of Spatial-Temporal Consistency Language STeC.
Proceedings of the 2014 Theoretical Aspects of Software Engineering Conference, 2014

Coalgebraic Semantic Model for the Clock Constraint Specification Language.
Proceedings of the Formal Techniques for Safety-Critical Systems, 2014

Execution of heterogeneous models for thermal analysis with a multi-view approach.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

2013
Scenario-based verification in presence of variability using a synchronous approach.
Frontiers Comput. Sci., 2013

Hybrid MARTE statecharts.
Frontiers Comput. Sci., 2013

Reifying Concurrency for Executable Metamodeling.
Proceedings of the Software Language Engineering - 6th International Conference, 2013

Verifying MARTE/CCSL Mode Behaviors Using UPPAAL.
Proceedings of the Software Engineering and Formal Methods - 11th International Conference, 2013

Power consumption analysis using multi-view modeling.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Safe CCSL specifications and marked graphs.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

Two Semantic Models for Clock Relations in the Clock Constraint Specification Language.
Proceedings of the Information and Communication Technologies in Education, Research, and Industrial Applications, 2013

Clocks Model for Specification and Analysis of Timing in Real-Time Embedded Systems.
Proceedings of the 9th International Conference on ICT in Education, 2013

Improving the Efficiency of Synchronized Product with Infinite Transition Systems.
Proceedings of the Information and Communication Technologies in Education, Research, and Industrial Applications, 2013

Lazy Parallel Synchronous Composition of Infinite Transition Systems.
Proceedings of the 9th International Conference on ICT in Education, 2013

UML Profile for MARTE: Time Model and CCSL.
Proceedings of the 9th International Conference on ICT in Education, 2013

Boundness Issues in CCSL Specifications.
Proceedings of the Formal Methods and Software Engineering, 2013

Tool Support for the Analysis of TADL2 Timing Constraints Using TimeSquare.
Proceedings of the 2013 18th International Conference on Engineering of Complex Computer Systems, 2013

Analysis Support for TADL2 Timing Constraints on EAST-ADL Models.
Proceedings of the Software Architecture - 7th European Conference, 2013

Schedulability Analysis with CCSL Specifications.
Proceedings of the 20th Asia-Pacific Software Engineering Conference, 2013

2012
TimeSquare: Treat Your Models with Logical Time.
Proceedings of the Objects, Models, Components, Patterns - 50th International Conference, 2012

Formal Specification of Hybrid MARTE Statecharts.
Proceedings of the Sixth International Symposium on Theoretical Aspects of Software Engineering, 2012

Automatic generation of observers from MARTE/CCSL.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Multi-view Power Modeling Based on UML, MARTE and SysML.
Proceedings of the 38th Euromicro Conference on Software Engineering and Advanced Applications, 2012

2011
Logical time: specification vs. implementation.
ACM SIGSOFT Softw. Eng. Notes, 2011

Logical Time and Temporal Logics: Comparing UML MARTE/CCSL and PSL.
Proceedings of the Eighteenth International Symposium on Temporal Representation and Reasoning, 2011

Verification of MARTE/CCSL Time Requirements in Promela/SPIN.
Proceedings of the 16th IEEE International Conference on Engineering of Complex Computer Systems, 2011

An Efficient Modeling and Execution Framework for Complex Systems Development.
Proceedings of the 16th IEEE International Conference on Engineering of Complex Computer Systems, 2011

A Model-Based Approach for Reconciliation of Polychronous Execution Traces.
Proceedings of the 37th EUROMICRO Conference on Software Engineering and Advanced Applications, SEAA 2011, Oulu, Finland, August 30, 2011

Modeling Timing Requirements in Problem Frames Using CCSL.
Proceedings of the 18th Asia Pacific Software Engineering Conference, 2011

2010
Un processus automatique pour concevoir les profils UML. Un profil UML pour la modélisation multiniveau.
Tech. Sci. Informatiques, 2010

The clock constraint specification language for building timed causality models - Application to synchronous data flow graphs.
Innov. Syst. Softw. Eng., 2010

RT-simex: retro-analysis of execution traces.
Proceedings of the 18th ACM SIGSOFT International Symposium on Foundations of Software Engineering, 2010

VHDL Observers for Clock Constraint Checking.
Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

Polychronous Analysis of Timing Constraints in UML MARTE.
Proceedings of the 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2010

Logical Time at Work: Capturing Data Dependencies and Platform Constraints.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

The Time Model of Logical Clocks Available in the OMG MARTE Profile.
Proceedings of the Synthesis of Embedded Software, 2010

Logical Time in Model-Driven Engineering.
, 2010

Temps Logique pour l'ingénierie dirigée par le modèles (Logical Time in Model-Driven Engineering).
, 2010

2009
An Automated Process for Implementing Multilevel Domain Models.
Proceedings of the Software Language Engineering, Second International Conference, 2009

Specification and verification of time requirements with CCSL and Esterel.
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009

Marte CCSL to Execute East-ADL Timing Requirements.
Proceedings of the 2009 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2009

On the Semantics of UML/MARTE Clock Constraints.
Proceedings of the 2009 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2009

Executing AADL Models with UML/MARTE.
Proceedings of the 14th IEEE International Conference on Engineering of Complex Computer Systems, 2009

IP-XACT components with abstract time characterization.
Proceedings of the Forum on specification and Design Languages, 2009

2008
Clock constraint specification language: specifying clock constraints with UML/MARTE.
Innov. Syst. Softw. Eng., 2008

MARTE: a profile for RT/E systems modeling, analysis-<i>and simulation</i>?
Proceedings of the 1st International Conference on Simulation Tools and Techniques for Communications, 2008

Dealing with AADL End-to-End Flow Latency with UML MARTE.
Proceedings of the 13th International Conference on Engineering of Complex Computer Systems (ICECCS 2008), March 31 2008, 2008

Event-Triggered vs. Time-Triggered Communications with UML MARTE.
Proceedings of the Forum on specification and Design Languages, 2008

MARTE vs. AADL for Discrete-Event and Discrete-Time Domains.
Proceedings of the Languages for Embedded Systems and their Applications, 2008

2007
A multiform time approach to real-time system modeling; Application to an automotive system.
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

Multiform Time in UML for Real-time Embedded Applications.
Proceedings of the 13th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2007), 2007

Modeling Time(s).
Proceedings of the Model Driven Engineering Languages and Systems, 2007

Modeling of immediate vs. delayed data communications: from AADL to UML Marte.
Proceedings of the Forum on specification and Design Languages, 2007

2006
From UML to Petri Nets for non functional Property Verification.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

2003
Simulation of a computer architecture for quantum chromodynamics calculations.
ACM Crossroads, 2003

2000
Concurrent Control Systems: From Grafcet to VHDL.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

SEP: Simulation framework to evaluate digital hardware architectures.
Proceedings of the 14<sup>th</sup> European Simulation Multiconference, 2000

1999
Esterel and Java in an Object-Oriented Modelling and Simulation Framework for Heterogeneous Software and Hardware Systems The SEP Approach.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

1998
Hardware Architecture Modelling Using an Object-Oriented Method.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

Hardware Modelling and Simulation Using an Object-Oriented Method.
Proceedings of the 12<sup>th</sup> European Simulation Multiconference - Simulation, 1998


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