Frédéric Bancel

According to our database, Frédéric Bancel authored at least 11 papers between 1993 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Securing Scan Control in Crypto Chips.

David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre

J. Electron. Test., 2007

Robustness of circuits under delay-induced faults : test of AES with the PAFI tool.

Olivier Faurax, Assia Tria, Laurent Freund, Frédéric Bancel

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

2006

Scan Pattern Watermarking.

David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre

Proceedings of the 7th Latin American Test Workshop, 2006

Securing embedded programmable gate arrays in secure circuits.

Nicolas Valette, Lionel Torres, Gilles Sassatelli, Frédéric Bancel

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Secure Scan Techniques: A Comparison.

David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A secure scan design methodology.

David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Integration of Reconfigurable Logic on Secure Circuits.

Nicolas Valette, Lionel Torres, Frédéric Bancel, Nicolas Bérard

Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Test control for secure scan designs.

David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre

Proceedings of the 10th European Test Symposium, 2005

2004

Scan Design and Secure Chip.

David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

1993

A DFT Technique to Improve ATPG Efficiency for Sequential Circuits.

Yves Bertrand, Frédéric Bancel, Michel Renovell

Proceedings of the Sixth International Conference on VLSI Design, 1993

Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits.

Yves Bertrand, Frédéric Bancel, Michel Renovell

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993