Fred J. Meyer
According to our database1,
Fred J. Meyer
authored at least 55 papers
between 1988 and 2006.
Collaborative distances:
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Bibliography
2006
IEEE Trans. Instrum. Meas., 2006
2005
IEEE Trans. Instrum. Meas., 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
IEEE Trans. Instrum. Meas., 2004
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
2003
IEEE Trans. Reliab., 2003
Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment.
IEEE Trans. Instrum. Meas., 2003
IEEE Trans. Computers, 2003
IEEE Trans. Computers, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
IEEE Des. Test Comput., 2002
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2001
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Computers, 2000
Diagnosing the Interconnect of Bus-Connected Multi-RAM Systems under Restricted and General Fault Models.
Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000
Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping.
Proceedings of the Parallel and Distributed Processing, 2000
1999
Test generation and scheduling for layout-based detection of bridge faults in interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 1999
J. Electron. Test., 1999
Guest Editors' Introduction: DRAM Architecture and Testing.
IEEE Des. Test Comput., 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999
Proceedings of the Digest of Papers: FTCS-29, 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
ACM Trans. Design Autom. Electr. Syst., 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Using Virtual Links for Reliable Information Retrieval Across Point-to-Point Networks.
Proceedings of the Digest of Papers: FTCS-27, 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
1993
Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model.
IEEE Trans. Very Large Scale Integr. Syst., 1993
1991
1989
1988