Fred Chen
According to our database1,
Fred Chen
authored at least 22 papers
between 2001 and 2017.
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Bibliography
2017
J. Oper. Res. Soc., 2017
2013
Why Analog-to-Information Converters Suffer in High-Bandwidth Sparse Signal Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Energy-Aware Design of Compressed Sensing Systems for Wireless Sensors Under Performance and Reliability Constraints.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors.
IEEE J. Solid State Circuits, 2012
Performance trade-offs and design limitations of analog-to-information converter front-ends.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
2011
Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications.
IEEE J. Solid State Circuits, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A signal-agnostic compressed sensing acquisition system for wireless and implantable sensors.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
A Modeling and exploration framework for interconnect network design in the nanometer era.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
2007
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2005
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery.
IEEE J. Solid State Circuits, 2005
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2003
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell.
IEEE J. Solid State Circuits, 2003
2001
A design environment for high throughput, low power dedicated signal processing systems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001