Frank Vater
According to our database1,
Frank Vater
authored at least 19 papers
between 2007 and 2024.
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Bibliography
2024
A 130-GHz Bandwidth 61-dBOhm Variable-Gain Differential Linear TIA in a 130-nm SiGe: C BiCMOS Technology.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2024
2019
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019
2017
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017
2015
Proceedings of the Security and Privacy in Communication Networks, 2015
Proceedings of the 45. Jahrestagung der Gesellschaft für Informatik, Informatik, Energie und Umwelt, INFORMATIK 2015, Cottbus, Germany, September 28, 2015
2013
Proceedings of the 2013 International Symposium on System on Chip, 2013
2012
Proceedings of the IEEE 25th International SOC Conference, 2012
Towards Strong Security in Embedded and Pervasive Systems: Energy and Area Optimized Serial Polynomial Multipliers in GF(2k).
Proceedings of the 5th International Conference on New Technologies, 2012
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
2011
Combining Multiplication Methods with Optimized Processing Sequence for Polynomial Multiplier in GF(2 k ).
Proceedings of the Research in Cryptology - 4th Western European Workshop, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Hybrid Simulation Environment for rapid MSP430 system design test and validation using MSPsim and SystemC.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
KSII Trans. Internet Inf. Syst., 2010
2009
Proceedings of the 3rd International Conference on Pervasive Computing Technologies for Healthcare, 2009
Proceedings of the Information, Security and Cryptology, 2009
2008
Proceedings of the Wired/Wireless Internet Communications, 6th International Conference, 2008
2007
An Area Efficient Realisation of AES for Wireless Devices (Eine flächeneffiziente AES Hardwarerealisierung für drahtlose Geräte).
it Inf. Technol., 2007
Combinatorial Logic Circuitry as Means to Protect Low Cost Devices Against Side Channel Attacks.
Proceedings of the Information Security Theory and Practices. Smart Cards, 2007