Frank Schirrmeister

Orcid: 0009-0002-8119-1779

According to our database1, Frank Schirrmeister authored at least 14 papers between 1993 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Addressing DRAM Performance Analysis Challenges for Network-on-Chip (NoC) Design.
Proceedings of the International Symposium on Memory Systems, 2023

2022
Guest Editorial: Thematic Section on Applications of Emerging Computing Technologies in Smart Manufacturing and Industry 4.0.
IEEE Trans. Emerg. Top. Comput., 2022

2017
Hardware/Software Codesign Across Many Cadence Technologies.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

2014
Panel: Future SoC verification methodology: UVM evolution or revolution?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012
Virtual platforms: Breaking new grounds.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Virtual Manycore platforms: Moving towards 100+ processor cores.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Virtual prototypes for software-dominated communication system designs.
IEEE Commun. Mag., 2010

Application specific processor design: Architectures, design methods and tools.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009
Software Standards for the Multicore Era.
IEEE Micro, 2009

2006
System-level exploration tools for MPSoC designs.
Proceedings of the 43rd Design Automation Conference, 2006

2002
A Design Chain for Embedded Systems.
Computer, 2002

2000
System Level Design Using C++.
Proceedings of the 2000 Design, 2000

1999
Methodology and technology for virtual component driven hardware/software co-design on the system-level.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1993
Realization of a real time phasecorrelation chipset used in a hierarchical two step HDTV motion vector estimator.
Proceedings of the International Conference on Application-Specific Array Processors, 1993


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