François Verdier

Orcid: 0000-0001-5038-4565

According to our database1, François Verdier authored at least 51 papers between 1992 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Accelerating Blockchain Applications on IoT Architecture Models - Solutions and Drawbacks.
Distributed Ledger Technol. Res. Pract., June, 2024

A Fair Crowd-Sourced Automotive Data Monetization Approach Using Substrate Hybrid Consensus Blockchain.
Future Internet, May, 2024

Toward the Conception of a Multichain to Meet Users' Future Needs: A Design Science Research Approach to Digital Servitization in the Automotive Industry.
IEEE Trans. Engineering Management, 2024

2023
A New Design for Self-Encryption.
Proceedings of the 22nd IEEE International Conference on Trust, 2023

CUBA: An Evolutionary Consortium Oriented Distributed Ledger Byzantine Consensus Algorithm.
Proceedings of the Distributed Computing and Artificial Intelligence, 2023

Virtuous Data Monetisation Cycle: A Hybrid Consensus Substrate Automotive Consortium Blockchain Solution.
Proceedings of the Blockchain and Applications, 5th International Congress, 2023

Communicate Vehicle Accident Data to Blockchain for Secure and Reliable Record-Keeping Using Android Automotive Application.
Proceedings of the Fifth International Conference on Blockchain Computing and Applications, 2023

2022
Blockchains Accesses for Low-Power Embedded Devices using LoRaWAN.
Proceedings of the 12th International Conference on the Internet of Things, 2022

2021
Experimental Scalability Study of Consortium Blockchains with BFT Consensus for IoT Automotive Use Case.
Proceedings of the SenSys '21: The 19th ACM Conference on Embedded Networked Sensor Systems, Coimbra, Portugal, November 15, 2021

Expand Reuse Strategy to ESL Power Modeling in SystemC/TLM.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Choice of Ethereum Clients for Private Blockchain: Assessment from Proof of Authority Perspective.
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2021

A Blockchain cloud architecture deployment for an industrial IoT use case.
Proceedings of the 2021 IEEE International Conference on Omni-Layer Intelligent Systems, 2021

2020
Toward unsupervised Human Activity Recognition on Microcontroller Units.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

A True Decentralized Implementation Based on IoT and Blockchain: a Vehicle Accident Use Case.
Proceedings of the 2020 International Conference on Omni-layer Intelligent Systems, 2020

2019
Energy consumption minimization on LoRaWAN sensor network by using an Artificial Neural Network based application.
Proceedings of the IEEE Sensors Applications Symposium, 2019

IoT Devices Hardware Modeling for Executing Blockchain and Smart Contracts Applications.
Proceedings of the 16th IEEE/ACS International Conference on Computer Systems and Applications, 2019

2018
Mobile Terminals System-Level Memory Exploratio for Power and Performance Optimization.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Energy Saving in a Wireless Sensor Network by Data Prediction by using Self-Organized Maps.
Proceedings of the 9th International Conference on Ambient Systems, 2018

2017
Power and performance aware electronic system level design.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

A framework for system level low power design space exploration.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Towards the verification of industrial communication protocols through a simulation environment based on QEMU and systemC.
Proceedings of the ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems, 2016

Wireless sensor network protocol property validation through the system's simulation in a dedicated framework.
Proceedings of the 10th International Conference on Signal Processing and Communication Systems, 2016

An ESL framework for low power architecture design space exploration.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
A methodology for inserting clock-management strategies in transaction-level models of systemon- chips.
Proceedings of the 2015 Forum on Specification and Design Languages, 2015

Network-Aware Virtual Platform for the Verification of Embedded Software for Communications.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
Very fast co-simulation model and accurate on-the-fly performance estimation methodology for heterogeneous MPSoC.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Multi-shape tasks scheduling for online multitasking on FPGAs.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

MRAPI resource management layer on reconfigurable systems-on-chip.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

MRAPI Implementation for Heterogeneous Reconfigurable Systems-on-Chip.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

2012
High-level model of sensor architecture for hardware and software design space exploration.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

2010
Low-complexity decoding for non-binary LDPC codes in high order fields.
IEEE Trans. Commun., 2010

2009
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms.
Int. J. Reconfigurable Comput., 2009

Run-Time HW/SW Scheduling of Data Flow Applications on Reconfigurable Architectures.
EURASIP J. Embed. Syst., 2009

Multiprocessor Task Migration Implementation in a Reconfigurable Platform.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2008
Using High-Level RTOS Models for HW/SW Embedded Architecture Exploration: Case Study on Mobile Robotic Vision.
EURASIP J. Embed. Syst., 2008

Dynamic Adaptation of Hardware-Software Scheduling for Reconfigurable System-on-Chip.
Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Split non-binary LDPC codes.
Proceedings of the 2008 IEEE International Symposium on Information Theory, 2008

Towards a Common HW/SW Interface-Centric and Component-Oriented Specification and Design Methodology.
Proceedings of the Forum on specification and Design Languages, 2008

Mapping Semantics of CORBA IDL and GIOP to Open Core Protocol for Portability and Interoperability of SDR Waveform Components.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Low-Complexity, Low-Memory EMS Algorithm for Non-Binary LDPC Codes.
Proceedings of IEEE International Conference on Communications, 2007

Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
A Low-Cost Parallel Scalable FPGA Architecture for Regular and Irregular LDPC Decoding.
IEEE Trans. Commun., 2006

Towards a SystemC TLM based Methodology for Platform Design and IP Reuse: Application to Software Defined Radio.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Conception d'architectures embarquées : des décodeurs LDPC aux systèmes sur puce reconfigurables. (The design of embedded architectures: from decoding LDPC to reconfigurable systems on chip).
, 2006

2005
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

2004
SOC and RTOS: Managing IPs and Tasks Communications.
Proceedings of the Field Programmable Logic and Application, 2004

2000
Fast Stable Matching Algorithm using Asynchronous Parallel Programming Model.
Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000

1998
A High Level Synthesis System for VLSI Image Processing Applications.
VLSI Design, 1998

1992
A high level synthesis algorithm including control constraints.
Microprocess. Microprogramming, 1992


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