A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode.

[BibT_eX]

[DOI]

David Bol

Maxime Schramme

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A 0.4-V 0.66-fJ/Cycle Retentive True-Single-Phase-Clock 18T Flip-Flop in 28-nm Fully-Depleted SOI CMOS.

[BibT_eX]

[DOI]

François Stas

David Bol

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017

SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

A 0.4V 0.08fJ/cycle retentive True-Single-Phase-Clock 18T Flip-Flop in 28nm FDSOI CMOS.

[BibT_eX]

[DOI]

François Stas

David Bol

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits.

[BibT_eX]

[DOI]

François Stas

David Bol

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016

SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools.

[BibT_eX]

[DOI]