François Marc
According to our database1,
François Marc
authored at least 31 papers
between 2000 and 2022.
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On csauthors.net:
Bibliography
2022
Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
2021
Electro-Thermal Limitations and Device Degradation of SiGe HBTs with Emphasis on Circuit Performance.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2021
2020
3D logic cells design and results based on Vertical NWFET technology including tied compact model.
CoRR, 2020
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.
Proceedings of the VLSI-SoC: Design Trends, 2020
2019
Impact of SiGe HBT hot-carrier degradation on the broadband amplifier output supply current.
Proceedings of the 49th European Solid-State Device Research Conference, 2019
2018
Multiscaled Simulation Methodology for Neuro-Inspired Circuits Demonstrated with an Organic Memristor.
IEEE Trans. Multi Scale Comput. Syst., 2018
Simulation and modelling of long term reliability of digital circuits implemented in FPGA.
Microelectron. Reliab., 2018
Influence of temperature of storage, write and read operations on multiple level cells NAND flash memories.
Microelectron. Reliab., 2018
2017
Proceedings of the 28th European Symposium on the reliability of electron devices, failure physics and analysis.
Microelectron. Reliab., 2017
2016
Microelectron. Reliab., 2016
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016
2015
Design and implementation of a low cost test bench to assess the reliability of FPGA.
Microelectron. Reliab., 2015
2013
J. Electron. Test., 2013
2012
J. Low Power Electron., 2012
Relation between HCI-induced performance degradation and applications in a RISC processor.
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Microelectron. Reliab., 2011
Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design.
Microelectron. Reliab., 2011
2010
Microelectron. Reliab., 2010
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010
2009
Electrical aging behavioral modeling for reliability analyses of ionizing dose effects on an n-MOS simple current mirror.
Microelectron. Reliab., 2009
2007
2006
Proceedings of the Forum on specification and Design Languages, 2006
2004
Microelectron. Reliab., 2004
2003
Ageing simulation of MOSFET circuit using a VHDL-AMS behavioural modelling: an experimental case study.
Microelectron. Reliab., 2003
Proceedings of the Forum on specification and Design Languages, 2003
2002
Contribution to ageing simulation of complex analogue circuit using VHDL-AMS behavioural modelling language.
Microelectron. Reliab., 2002
2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000